AD9396KSTZ-100 Analog Devices Inc, AD9396KSTZ-100 Datasheet - Page 25

• Manufacturer Part Number: AD9396KSTZ-100
• Description: IC INTERFACE 100MHZ DVI 100LQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9396KSTZ-100

• Applications: Video
• Interface: Analog, DVI
• Voltage - Supply: 3.15 V ~ 3.47 V
• Package / Case: 100-LQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Hex
Address
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
Read/Write
or Read Only
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read
Bits
[3:2]
[1]
[0]
[7]
[6]
[3]
[2:1]
[0]
[7]
[6]
[4]
[3]
[2:0]
[7:2]
[1:0]
[7:0]
[3:0]
[7:0]
[3:0]
[7:0]
[7]
[6]
[5]
[3]
[2:0]
Default
Value
****00**
******1*
*******0
0*******
*0******
****1***
*****00*
*******0
1*******
*0******
***0****
****0***
*****000
011000**
******01
00000100
****0101
00000000
****0010
11010000
0*******
*0******
**0*****
****0***
*****000
Register Name
Output Mode
Primary Output
Enable
Secondary
Output Enable
Output Three-
State
SOG Three-State
Power-Down Pin
Polarity
Power-Down Pin
Function
Power-Down
Auto Power-
Down Enable
HDCP A0
BT656 EN
Force DE
Generation
Interlace Offset
VS Delay
HS Delay MSB
HS Delay
Line Width MSB
Line Width
Screen Height
MSB
Screen Height
Test 1
TMDS Sync
Detect
TMDS Active
HDCP Keys Read
DVI Quality
Rev. 0 | Page 25 of 48
Description
Selects which pins the data comes out on.
00 = 4:4:4 mode (normal).
01 = 4:2:2 + DDR 4:2:2 on blue.
10 = DDR 4:4:4 + DDR 4:2:2 on blue.
Enables primary output.
Enables secondary output (DDR 4:2:2 in Output Mode 1 and
Mode 2).
Three-states the outputs.
Three-states the SOG output.
Sets polarity of power-down pin.
0 = active low.
1 = active high.
Selects the function of the power-down pin.
00 = power-down.
01 = power-down and three-state SOG.
10 = three-state outputs only.
11 = three-state outputs and SOG.
0 = normal.
1 = power-down.
0 = disable auto low power state.
1 = enable auto low power state.
Sets the LSB of the address of the HDCP I
second receiver in a dual-link configuration.
0 = use internally generated MCLK.
1 = use external MCLK input.
Enables EAV/SAV codes to be inserted into the video output data.
Allows use of the internal DE generator in DVI mode.
Sets the difference (in HSYNCs) in field length between Field 0 and
Field 1.
Sets the delay (in lines) from VSYNC leading edge to the start of
active video.
MSB, Register 0x29.
Sets the delay (in pixels) from HSYNC leading edge to the start of
active video.
MSB, Register 0x2B.
Sets the width of the active video line (in pixels).
MSB, Register 0x2D.
Sets the height of the active screen (in lines).
Must be written to 1 for proper operation.
Detects a TMDS DE.
Detects a TMDS clock.
Returns 1 when read of EEPROM keys is successful.
Returns quality number based on DE edges.
2
C. Set to 1 only for a
AD9396