MT36HTF51272PZ-80EH1 Micron Technology Inc, MT36HTF51272PZ-80EH1 Datasheet - Page 13

• Manufacturer Part Number: MT36HTF51272PZ-80EH1
• Description: MODULE DDR2 SDRAM 4GB 240FDIMM
• Manufacturer: Micron Technology Inc
• Series: -r

Specifications of MT36HTF51272PZ-80EH1

• Memory Type: DDR2 SDRAM
• Memory Size: 4GB
• Speed: 800MT/s
• Features: -
• Package / Case: 240-RDIMM
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 12: DDR2 I
Values shown for MT47H256M4 DDR2 SDRAM only and are computed from values specified in the 1Gb (256 Meg x 4) com-
ponent data sheet
Table 13: DDR2 I
Values shown for MT47H256M4 DDR2 SDRAM only and are computed from values specified in the 2Gb (256 Meg x 4) com-
ponent data sheet
PDF: 09005aef83d65c27
htf36c256_512_1gx72pz.pdf - Rev. D 10/10 EN
Parameter
Active power-down current: All device banks open;
(I
Data bus inputs are floating
Active standby current: All device banks open;
(I
trol and address bus inputs are switching; Data bus inputs are switching
Operating burst write current: All device banks open; Continuous burst writes;
BL = 4, CL = CL (I
CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching;
Data bus inputs are switching
Operating burst read current: All device banks open; Continuous burst read,
I
=
are switching; Data bus inputs are switching
Burst refresh current:
val; CKE is HIGH, S# is HIGH between valid commands; Other control and address
bus inputs are switching; Data bus inputs are switching
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and address
bus inputs are floating; Data bus inputs are floating
Operating bank interleave read current: All device banks interleaving reads,
I
t
commands; Address bus inputs are stable during deselects; Data bus inputs are
switching
Parameter
Operating one bank active-precharge current:
t
bus inputs are switching; Data bus inputs are switching
Operating one bank active-read-precharge current: I
CL (I
(I
switching; Data pattern is same as I
OUT
OUT
RC (I
RAS =
DD
DD
DD
t
RP (I
); CKE is LOW; Other control and address bus inputs are stable;
),
); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are
DD
= 0mA; BL = 4, CL = CL (I
= 0mA; BL = 4, CL = CL (I
DD
t
RP =
), AL = 0;
DD
t
),
RAS MIN (I
); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs
t
RRD =
t
RP (I
t
DD
DD
t
CK =
RRD (I
DD
); CKE is HIGH, S# is HIGH between valid commands; Other con-
), AL = 0;
DD
DD
); CKE is HIGH, S# is HIGH between valid commands; Address
Notes:
t
CK (I
Specifications and Conditions – 4GB (Die Revisions E and G) (Continued)
Specifications and Conditions – 4GB (Die Revision H)
DD
t
CK =
),
DD
t
t
RCD =
DD
DD
CK =
),
t
CK (I
1. Value calculated as one module rank in this operating condition. All other module ranks
2. Value calculated reflects all module ranks in this operating condition.
), AL = 0;
), AL =
t
RC =
in I
t
CK (I
t
DD
DD4W
2Gb, 4GB, 8GB (x72, ECC, DR) 240-Pin DDR2 SDRAM RDIMM
RCD (I
DD2P
t
); REFRESH command at every
RC (I
t
RCD (I
DD
t
CK =
),
DD
(CKE LOW) mode.
DD
t
); CKE is HIGH, S# is HIGH between valid
RAS =
),
DD
t
t
CK (I
) - 1 ×
RAS =
t
CK =
t
t
RAS MAX (I
DD
CK =
t
t
),
CK (I
RAS MIN (I
t
CK =
t
t
CK (I
RAS =
t
CK (I
OUT
DD
13
t
DD
);
CK
= 0mA; BL = 4, CL =
DD
DD
t
t
),
RAS MAX (I
CK =
),
DD
),
t
RAS =
t
t
RC =
),
RP =
t
Fast PDN exit
MR[12] = 0
Slow PDN exit
MR[12] = 1
RFC (I
t
t
CK (I
RCD =
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
t
t
RC (I
RAS MAX
RP (I
DD
DD
DD
) inter-
),
t
RCD
),
DD
DD
t
RC =
t
),
RP
);
Symbol
Symbol
I
I
I
I
DD4W
DD3N
I
I
I
I
I
DD3P
DD4R
DD5
DD6
DD7
DD0
DD1
2
2
1
1
1
2
1
2
1
© 2009 Micron Technology, Inc. All rights reserved.
I
-80E/
-80E/
DD
1440
2160
2736
2736
8460
6156
1296
1476
-800
-800
360
252
Specifications
1080
1980
2286
2286
7740
5166
1206
1386
-667
-667
360
252
Units
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA