PCA9558PW,118 NXP Semiconductors, PCA9558PW,118 Datasheet - Page 5
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PCA9558PW,118
Manufacturer Part Number
PCA9558PW,118
Description
IC I2C SMBUS 8BIT I/O 28TSSOP
Manufacturer
NXP Semiconductors
Datasheet
1.PCA9558PW112.pdf
(27 pages)
Specifications of PCA9558PW,118
Package / Case
28-TSSOP
Applications
PC's, PDA's
Interface
I²C
Voltage - Supply
3 V ~ 3.6 V
Mounting Type
Surface Mount
Logic Family
PCA9558
Number Of Lines (input / Output)
8.0 / 8.0
Propagation Delay Time
21 ns
Operating Supply Voltage
3 V to 3.6 V
Operating Temperature Range
0 C to + 70 C
Input Voltage
5 V
Logic Type
I2C, SMBus
Maximum Clock Frequency
400 KHz
Mounting Style
SMD/SMT
Number Of Input Lines
8.0
Number Of Output Lines
8.0
Output Voltage
5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
935269433118
PCA9558PW-T
PCA9558PW-T
PCA9558PW-T
PCA9558PW-T
NXP Semiconductors
7. Functional description
PCA9558_4
Product data sheet
7.1 I
Table 2.
Refer to
Communicating with this device is initiated by sending a valid address on the I
address format (see
a 1-bit read/write value which determines the direction of the data transfer.
Following the address and acknowledge bit are 8 data bits which, depending on the
read/write bit in the address, will read data from or write data to the EEPROM. Data will be
written to the register if the read/write bit is logic 0 and the WP input is logic 0. Data will be
read from the register if the bit is logic 1. The four high-order bits are latched outputs,
while the four low order bits are multiplexed outputs
Remark: To ensure data integrity, the EEPROM must be internally write protected when
V
operating levels.
Symbol
MUX_SELECT
MUX_OUTE
MUX_OUTD
MUX_OUTC
MUX_OUTB
MUX_OUTA
NON_MUXED_OUT
MUX_OUT_LOW
WP
V
2
Fig 3.
Fig 4.
DD
DD
C-bus interface
to the I
Figure 1 “Block diagram of
I
Command byte
2
Pin description
C-bus address byte
2
C-bus is powered down or V
Figure
Pin
19
20
21
22
23
24
25
26
27
28
Rev. 04 — 14 April 2009
…continued
3) has 6 fixed bits and one user-programmable bit followed by
MSB
D7
1
D6
0
Description
active LOW select of MUX_INx inputs or EEPROM contents
for MUX_OUTx outputs
open-drain multiplexed output E
open-drain multiplexed output D
open-drain multiplexed output C
open-drain multiplexed output B
open-drain multiplexed output A
open-drain outputs from non-volatile memory
active LOW control forces all MUX outputs to logic 0
active HIGH EEPROM write protect
power supply (3.0 V to 3.6 V)
PCA9558”.
D5
0
fixed
DD
D4
1
to the component is dropped below normal
D3
1
D2
1
(Figure
002aad367
A0
002aad368
D1
hardware
selectable
LSB
R/W
D0
8-bit I
5).
2
C-bus/SMBus I/O port
PCA9558
© NXP B.V. 2009. All rights reserved.
2
C-bus. The
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