PCA9558PW,118 NXP Semiconductors, PCA9558PW,118 Datasheet - Page 12

• Manufacturer Part Number: PCA9558PW,118
• Description: IC I2C SMBUS 8BIT I/O 28TSSOP
• Manufacturer: NXP Semiconductors

Specifications of PCA9558PW,118

• Package / Case: 28-TSSOP
• Applications: PC's, PDA's
• Interface: I²C
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Logic Family: PCA9558
• Number Of Lines (input / Output): 8.0 / 8.0
• Propagation Delay Time: 21 ns
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: 0 C to + 70 C
• Input Voltage: 5 V
• Logic Type: I2C, SMBus
• Maximum Clock Frequency: 400 KHz
• Mounting Style: SMD/SMT
• Number Of Input Lines: 8.0
• Number Of Output Lines: 8.0
• Output Voltage: 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935269433118; PCA9558PW-T; PCA9558PW-T

NXP Semiconductors
PCA9558_4
Product data sheet
Fig 14. I
S
START condition
1
M bytes where M
2
C-bus page write operation to 256-byte EEPROM
0
slave address
7.1.3.3 256-byte write operation (I
7.1.3.4 256-byte read operation (I
0
1
1
A write operation to the 256-byte EEPROM requires that an address byte be written after
the command byte. This address points to the starting address in the EEPROM array. The
four LSBs of this address select a position on a 16-byte page register, the 4 MSBs select
which page register. The four LSBs will be auto-incremented after receipt of each byte of
data; in this manner, the entire page register can be written starting at any point. Up to
16 bytes of data may be sent to the PCA9558, followed by a STOP condition on the
I
condition, data within the address page will be overwritten and unpredictable results may
occur. See
After the STOP condition, the E/W cycle starts, and the parts will not respond to any
request to access the EEPROM array until the cycle finishes, approximately 4 ms.
A read operation is initiated in the same manner as a write operation, with the exception
that after the word address has been written, a REPEATED START condition is placed on
the I
entire address is incremented after the transmission of each byte, meaning that the entire
256-byte EEPROM array can be read at one time. See
1 A0 0
2
C-bus. If the master sends more than 16 bytes of data prior to generating a STOP
15.
R/W
2
C-bus, and the direction of communication is reversed. For a read operation, the
A
acknowledge
from slave
Figure
0
0
command code
0
14.
0
Rev. 04 — 14 April 2009
0
(cont.)
0
2
2
C-bus)
C-bus)
0
1
DATA N + 1
A
acknowledge
from slave
EEPROM address
Auto-Increment
word address
acknowledge
A
from slave
acknowledge
from slave
A
Figure
8-bit I
DATA N + M
15.
DATA N
Auto-Increment
2
word address
C-bus/SMBus I/O port
Auto-Increment
word address
PCA9558
© NXP B.V. 2009. All rights reserved.
A
A
acknowledge
from slave
acknowledge
from slave
002aad378
(cont.)
P
STOP
condition
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