PCA9558PW,118 NXP Semiconductors, PCA9558PW,118 Datasheet - Page 11

• Manufacturer Part Number: PCA9558PW,118
• Description: IC I2C SMBUS 8BIT I/O 28TSSOP
• Manufacturer: NXP Semiconductors

Specifications of PCA9558PW,118

• Package / Case: 28-TSSOP
• Applications: PC's, PDA's
• Interface: I²C
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Logic Family: PCA9558
• Number Of Lines (input / Output): 8.0 / 8.0
• Propagation Delay Time: 21 ns
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: 0 C to + 70 C
• Input Voltage: 5 V
• Logic Type: I2C, SMBus
• Maximum Clock Frequency: 400 KHz
• Mounting Style: SMD/SMT
• Number Of Input Lines: 8.0
• Number Of Output Lines: 8.0
• Output Voltage: 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935269433118; PCA9558PW-T; PCA9558PW-T

NXP Semiconductors
PCA9558_4
Product data sheet
Fig 12. I
Fig 13. I
S
START condition
2
2
1
C-bus write of 6-bit EEPROM
C-bus read of 6-bit EEPROM
S
START condition
7.1.3.1 6-bit write operation
7.1.3.2 6-bit read operation
0
7.1.3 EEPROM write operation
slave address
1
0
0
1
slave address
0
1
A write operation to the 6-bit EEPROM requires that an address byte be written after the
command byte. This address points to the 6-bit address space in the EEPROM array.
Upon receipt of this address, the PCA9558 waits for the next byte that will be written to the
EEPROM. The master then ends the transaction with a STOP condition on the I
See
After the STOP condition, the E/W cycle starts, and the parts will not respond to any
request to access the EEPROM array until the cycle finishes, approximately 4 ms.
A read operation is initiated in the same manner as a write operation, with the exception
that after the word address has been written a REPEATED START condition is placed on
the I
1
1 A0 0
2
Figure
1
C-bus and the direction of communication is reversed (see
R/W
1 A0 0
(cont.)
A
acknowledge
from slave
R/W
12.
0
A
S
(re)START
condition
acknowledge
from slave
0
command byte
0
1
0
0
0
0
Rev. 04 — 14 April 2009
slave address
command byte
0
0
0
0
1
1
acknowledge
from slave
0
1
0
(cont.) X
1
1 A0 1
acknowledge
0
from slave
1
A
R/W
0
1
A
A
data for 6-bit EEPROM
acknowledge
from slave
X d5 d4 d3 d2 d1 d0
1
EEPROM address
1
0
1
data from 6-bit EEPROM
1
0 d5 d4 d3 d2 d1 d0
1
EEPROM address
1
1
1
1
acknowledge
from slave
1
1
no acknowledge
8-bit I
1
1
acknowledge
from master
from slave
1
A
A
acknowledge
from slave
Figure
2
002aad376
(cont.)
1
P
STOP
condition
C-bus/SMBus I/O port
NA
A
programming begins
after STOP
PCA9558
(cont.)
002aad377
© NXP B.V. 2009. All rights reserved.
P
STOP
condition
13).
2
C-bus.
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