DS90CR484VJDX/NOPB National Semiconductor, DS90CR484VJDX/NOPB Datasheet - Page 11
DS90CR484VJDX/NOPB
Manufacturer Part Number
DS90CR484VJDX/NOPB
Description
IC DESERIALIZER 48BIT 100-TQFP
Manufacturer
National Semiconductor
Datasheet
1.DS90CR483VJDNOPB.pdf
(22 pages)
Specifications of DS90CR484VJDX/NOPB
Function
Serializer/Deserializer
Data Rate
5.38Gbps
Input Type
LVDS
Output Type
CMOS, TTL
Number Of Inputs
8
Number Of Outputs
48
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-10°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
*DS90CR484VJDX
*DS90CR484VJDX/NOPB
DS90CR484VJDX
*DS90CR484VJDX/NOPB
DS90CR484VJDX
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DS90CR484VJDX/NOPB
Manufacturer:
Texas Instruments
Quantity:
10 000
AC Timing Diagrams
C — Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max
TPPOS — Transmitter output pulse position (min and max)
RSKM ≥ Cable Skew (type, length) + LVDS Source Clock Jitter (cycle to cycle) + ISI (Inter-symbol interference)
C — Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max
RSKMD ≥ TPPOSvariance (d) + TJCC (output jitter)(f) + ISI (m)
See Applications Informations section for more details.
j
j
j
j
j
j
j
Cable Skew — typically 10 ps to 40 ps per foot, media dependent
TJCC — Cycle-to-cycle LVDS Output jitter (TJCC) is less than 100 ps (worse case estimate).
ISI is dependent on interconnect length; may be zero
See Applications Informations section for more details.
d = Tppos — Transmitter output pulse position (min and max)
f = TJCC — Cycle-to-cycle LVDS Output jitter (TJCC) is less than 100 ps (worse case estimate).
m = extra margin - assigned to ISI in long cable applications
FIGURE 13. Receiver Skew Margin (RSKM) without DESKEW
FIGURE 14. Receiver Skew Margin (RSKMD)with DESKEW
(Continued)
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