PCA9574PW,118 NXP Semiconductors, PCA9574PW,118 Datasheet - Page 21

• Manufacturer Part Number: PCA9574PW,118
• Description: IC I/O EXPANDER I2C 8B 16TSSOP
• Manufacturer: NXP Semiconductors

Specifications of PCA9574PW,118

• Package / Case: 16-TSSOP
• Interface: I²C, SMBus
• Number Of I /o: 8
• Interrupt Output: Yes
• Frequency - Clock: 400kHz
• Voltage - Supply: 1.1 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Includes: POR
• High Level Output Current: 1 mA
• Low Level Output Current: 3 mA
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 1.1 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Maximum Power Dissipation: 75 mW
• Mounting Style: SMD/SMT
• Number Of Circuits: Octal
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935285149118; PCA9574PW-T; PCA9574PW-T

NXP Semiconductors
13. Dynamic characteristics
Table 15.
V
[1]
[2]
[3]
PCA9574_2
Product data sheet
Symbol
f
t
t
t
t
t
t
t
t
t
t
t
t
t
Port timing
t
t
t
Interrupt timing
t
t
Reset
t
t
t
t
SCL
BUF
HD;STA
SU;STA
SU;STO
VD;ACK
HD;DAT
VD;DAT
SU;DAT
LOW
HIGH
f
r
SP
v(Q)
su(D)
h(D)
v(INT)
rst(INT)
w(rst)
rec(rst)
rst(SDA)
rst(GPIO)
DD
= 1.1 V to 3.6 V; V
t
t
C
VD;ACK
VD;DAT
b
= total capacitance of one bus line in pF.
= minimum time for SDA data out to be valid following SCL LOW.
= time for acknowledgement signal from SCL LOW to SDA (out) LOW.
Parameter
SCL clock frequency
bus free time between a STOP and
START condition
hold time (repeated) START condition
set-up time for a repeated START
condition
set-up time for STOP condition
data valid acknowledge time
data hold time
data valid time
data set-up time
LOW period of the SCL clock
HIGH period of the SCL clock
fall time of both SDA and SCL signals
rise time of both SDA and SCL signals
pulse width of spikes that must be
suppressed by the input filter
data output valid time
data input set-up time
data input hold time
valid time on pin INT
reset time on pin INT
reset pulse width
reset recovery time
SDA reset time
GPIO reset time
Dynamic characteristics
DD(IO)
= 1.1 V to 3.6 V; V
SS
= 0 V; T
Rev. 02 — 27 July 2009
8-bit I
Conditions
Figure 20
Figure 20
amb
2
C-bus and SMBus, level translating, low voltage GPIO
= 40 C to +85 C; unless otherwise specified.
[1]
[2]
Standard-mode
Min
300
250
150
4.7
4.0
4.7
4.0
0.3
4.7
4.0
0
0
1
6
0
-
-
-
-
-
-
-
-
I
2
C-bus
1000
Max
3.45
100
300
200
450
450
50
4
4
-
-
-
-
-
-
-
-
-
-
-
-
-
20 + 0.1C
20 + 0.1C
Fast-mode I
Min
100
150
1.3
0.6
0.6
0.6
0.1
1.3
0.6
50
0
0
1
6
0
-
-
-
-
-
-
PCA9574
b
b
© NXP B.V. 2009. All rights reserved.
[3]
[3]
2
C-bus
Max
400
300
300
200
450
450
0.9
50
4
4
-
-
-
-
-
-
-
-
-
-
-
-
-
21 of 32
ns
ns
Unit
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
s
s
s
s
s
s
s
s
s