PCA9574PW,118 NXP Semiconductors, PCA9574PW,118 Datasheet - Page 12

IC I/O EXPANDER I2C 8B 16TSSOP

PCA9574PW,118

Manufacturer Part Number
PCA9574PW,118
Description
IC I/O EXPANDER I2C 8B 16TSSOP
Manufacturer
NXP Semiconductors
Datasheet

Specifications of PCA9574PW,118

Package / Case
16-TSSOP
Interface
I²C, SMBus
Number Of I /o
8
Interrupt Output
Yes
Frequency - Clock
400kHz
Voltage - Supply
1.1 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Includes
POR
High Level Output Current
1 mA
Low Level Output Current
3 mA
Supply Voltage (max)
3.6 V
Supply Voltage (min)
1.1 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Maximum Power Dissipation
75 mW
Mounting Style
SMD/SMT
Number Of Circuits
Octal
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
935285149118
PCA9574PW-T
PCA9574PW-T
NXP Semiconductors
PCA9574_2
Product data sheet
7.5.8 Register 7 - Interrupt status register
7.6 Power-on reset
7.7 RESET input
7.8 Software reset
This register is read-only. It is used to identify the source of interrupt.
Remark: If the interrupts are masked, this register will return all zeros.
Table 12.
Legend: * default value.
When power is applied to V
a reset condition until V
and the PCA9574 registers and state machine will initialize to their default states. The
power-on reset typically completes the reset and enables the part by the time the power
supply is above V
supply, it is necessary to lower it below 0.2 V.
A reset can be accomplished by holding the RESET pin LOW for a minimum of t
PCA9574 registers and I
RESET input is once again HIGH.
The Software Reset Call allows all the devices in the I
state value through a specific formatted I
implies that the I
The Software Reset sequence is defined as following:
Bit
7
6
5
4
3
2
1
0
1. A START command is sent by the I
2. The reserved General Call I
3. The PCA9574 device(s) acknowledge(s) after seeing the General Call address
4. Once the General Call address has been sent and acknowledged, the master sends
is sent by the I
‘0000 0000’ (00h) only. If the R/W bit is set to logic 1 (read), no acknowledge is
returned to the I
1 byte. The value of the byte must be equal to 06h.The PCA9574 acknowledges this
value only. If the byte is not equal to 06h, the PCA9574 does not acknowledge it. If
more than 1 byte of data is sent, the PCA9574 does not acknowledge anymore.
Symbol
S0.7
S0.6
S0.5
S0.4
S0.3
S0.2
S0.1
S0.0
Register 7 - Interrupt status register (address 07h) bit description
2
POR
C-bus is functional and that there is no device hanging the bus.
2
C-bus master.
Access
read only
read only
read only
read only
read only
read only
read only
read only
2
. However, when it is required to reset the part by lowering the power
C-bus master.
DD
Rev. 02 — 27 July 2009
2
8-bit I
C-bus state machine will be held in their default state until the
has reached V
DD
, an internal Power-On Reset (POR) holds the PCA9574 in
2
2
Value
0*
0*
0*
0*
0*
0*
0*
0*
C-bus and SMBus, level translating, low voltage GPIO
C-bus address ‘0000 000’ with the R/W bit set to 0 (write)
2
C-bus master.
2
POR
Description
identifies source of interrupt
C-bus command. To be performed correctly, it
. At that point, the reset condition is released
2
C-bus to be reset to the power-up
PCA9574
© NXP B.V. 2009. All rights reserved.
w(rst)
12 of 32
. The

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