PIC32MX440F512H-80V/MR Microchip Technology, PIC32MX440F512H-80V/MR Datasheet - Page 73
![512 KB Flash, 32 KB RAM, USB-OTG, 80 MHz, 10-Bit ADC, DMA 64 QFN 9x9x0.9mm TUBE](/photos/40/62/406286/landingpagemicrochippic32_sml.jpg)
PIC32MX440F512H-80V/MR
Manufacturer Part Number
PIC32MX440F512H-80V/MR
Description
512 KB Flash, 32 KB RAM, USB-OTG, 80 MHz, 10-Bit ADC, DMA 64 QFN 9x9x0.9mm TUBE
Manufacturer
Microchip Technology
Series
PIC® 32MXr
Datasheet
1.TDGL001.pdf
(214 pages)
Specifications of PIC32MX440F512H-80V/MR
Processor Series
PIC32MX4xx
Core
MIPS
Data Bus Width
32 bit
Program Memory Type
Flash
Program Memory Size
512 KB
Data Ram Size
32 KB
Interface Type
USB, I2C, UART, RS-232, RS-485, SPI
Maximum Clock Frequency
80 MHz
Number Of Programmable I/os
5
Number Of Timers
5
Operating Supply Voltage
2.3 V to 3.6 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Package / Case
QFN-64
Operating Temperature Range
- 40 C to + 105 C
Supply Current (max)
10 mA
Core Processor
MIPS32® M4K™
Core Size
32-Bit
Speed
80MHz
Connectivity
I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
53
Eeprom Size
-
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Lead Free Status / Rohs Status
Details
- Current page: 73 of 214
- Download datasheet (5Mb)
TABLE 4-27:
TABLE 4-28:
Legend:
Note
Legend:
Note
6100
6120
6130
6100
6120
6130
6110
6110
1:
1:
PORTE
PORTE
TRISE
ODCE
TRISE
ODCE
LATE
LATE
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See
information.
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See
information.
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
PORTE REGISTERS MAP FOR PIC32MX320F128L, PIC32MX340F128L, PIC32MX360F256L, PIC32MX360F512L,
PIC32MX440F128L, PIC32MX460F256L AND PIC32MX460F512L DEVICES ONLY
PORTE REGISTERS MAP FOR PIC32MX320F032H, PIC32MX320F064H, PIC32MX320F128H, PIC32MX340F128H,
PIC32MX340F256H, PIC32MX340F512H, PIC32MX420F032H, PIC32MX440F128H, PIC32MX440F256H AND PIC32MX440F512H
DEVICES ONLY
31/15
31/15
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
30/14
30/14
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(1)
29/13
29/13
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
28/12
28/12
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
27/11
27/11
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
26/10
26/10
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRISE9
ODCE9
LATE9
25/9
RE9
25/9
—
—
—
—
—
—
—
—
—
—
—
—
TRISE8
ODCE8
LATE8
24/8
24/8
RE8
—
—
—
—
—
—
—
—
—
—
—
—
Bits
Bits
TRISE7
TRISE7
ODCE7
ODCE7
LATE7
LATE7
23/7
23/7
RE7
RE7
—
—
—
—
—
—
—
—
TRISE6
TRISE6
ODCE6
ODCE6
LATE6
LATE6
22/6
22/6
RE6
RE6
—
—
—
—
—
—
—
—
TRISE5
ODCE5
TRISE5
ODCE5
LATE5
LATE5
21/5
21/5
RE5
RE5
—
—
—
—
—
—
—
—
(1)
TRISE4
ODCE4
TRISE4
ODCE4
LATE4
LATE4
20/4
RE4
20/4
RE4
—
—
—
—
—
—
—
—
Section 12.1.1 “CLR, SET and INV Registers”
Section 12.1.1 “CLR, SET and INV Registers”
TRISE3
ODCE3
TRISE3
ODCE3
LATE3
LATE3
19/3
RE3
19/3
RE3
—
—
—
—
—
—
—
—
TRISE2
ODCE2
TRISE2
ODCE2
LATE2
LATE2
18/2
18/2
RE2
RE2
—
—
—
—
—
—
—
—
TRISE1
ODCE1
TRISE1
ODCE1
LATE1
LATE1
17/1
17/1
RE1
RE1
—
—
—
—
—
—
—
—
TRISE0
TRISE0
ODCE0
ODCE0
LATE0
LATE0
16/0
16/0
RE0
RE0
—
—
—
—
for more
—
—
—
—
for more
0000
03FF
0000
xxxx
0000
xxxx
0000
0000
0000
00FF
0000
xxxx
0000
xxxx
0000
0000
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