PIC32MX440F512H-80V/MR Microchip Technology, PIC32MX440F512H-80V/MR Datasheet - Page 67
![512 KB Flash, 32 KB RAM, USB-OTG, 80 MHz, 10-Bit ADC, DMA 64 QFN 9x9x0.9mm TUBE](/photos/40/62/406286/landingpagemicrochippic32_sml.jpg)
PIC32MX440F512H-80V/MR
Manufacturer Part Number
PIC32MX440F512H-80V/MR
Description
512 KB Flash, 32 KB RAM, USB-OTG, 80 MHz, 10-Bit ADC, DMA 64 QFN 9x9x0.9mm TUBE
Manufacturer
Microchip Technology
Series
PIC® 32MXr
Datasheet
1.TDGL001.pdf
(214 pages)
Specifications of PIC32MX440F512H-80V/MR
Processor Series
PIC32MX4xx
Core
MIPS
Data Bus Width
32 bit
Program Memory Type
Flash
Program Memory Size
512 KB
Data Ram Size
32 KB
Interface Type
USB, I2C, UART, RS-232, RS-485, SPI
Maximum Clock Frequency
80 MHz
Number Of Programmable I/os
5
Number Of Timers
5
Operating Supply Voltage
2.3 V to 3.6 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Package / Case
QFN-64
Operating Temperature Range
- 40 C to + 105 C
Supply Current (max)
10 mA
Core Processor
MIPS32® M4K™
Core Size
32-Bit
Speed
80MHz
Connectivity
I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
53
Eeprom Size
-
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Lead Free Status / Rohs Status
Details
- Current page: 67 of 214
- Download datasheet (5Mb)
TABLE 4-16:
Legend:
Note
32A0 DCH3CON
32B0 DCH3ECON
32C0
32D0 DCH3SSA
32E0 DCH3DSA
32F0 DCH3SSIZ
3260 DCH2DPTR
3270 DCH2CSIZ
3280 DCH2CPTR
3290
3300 DCH3DSIZ
3310 DCH3SPTR
3320 DCH3DPTR
3330 DCH3CSIZ
3340 DCH3CPTR
3350
1:
DCH2DAT
DCH3DAT
DCH3INT
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers except DCHxSPTR, DCHxDPTR and DCHxCPTR have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See
SET and INV Registers”
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
DMA CHANNELS 0-3 REGISTERS MAP FOR PIC32MX340FXXXX/360FXXXX/440FXXXX/460XXXX
DEVICES ONLY
31/15
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for more information.
30/14
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(1)
29/13
(CONTINUED)
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28/12
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CHSIRQ<7:0>
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27/11
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26/10
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25/9
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CHCHNS
24/8
CHSSA<31:0>
CHDSA<31:0>
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Bits
CFORCE
CHSDIE
CHSDIF
CHEN
23/7
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CABORT
CHSHIE
CHSHIF
CHAED
22/6
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CHDDIE
CHCHN
CHDDIF
PATEN
21/5
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SIRQEN
CHDHIE
CHDHIF
CHAEN
20/4
CHDPTR<7:0>
CHCPTR<7:0>
CHDPTR<7:0>
CHCPTR<7:0>
CHPDAT<7:0>
CHPDAT<7:0>
—
—
CHCSIZ<7:0>
—
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—
CHAIRQ<7:0>
—
—
CHDSIZ<7:0>
—
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—
CHCSIZ<7:0>
—
—
CHSSIZ<7:0>
CHSTR<7:0>
AIRQEN
CHBCIE
CHBCIF
19/3
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CHEDET
CHCCIE
CHCCIF
18/2
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CHTAIE
CHTAIF
17/1
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CHPRI<1:0>
Section 12.1.1 “CLR,
CHERIE 0000
CHERIF
16/0
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0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
00FF
FF00
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
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