PIC32MX440F512H-80V/MR Microchip Technology, PIC32MX440F512H-80V/MR Datasheet - Page 59
![512 KB Flash, 32 KB RAM, USB-OTG, 80 MHz, 10-Bit ADC, DMA 64 QFN 9x9x0.9mm TUBE](/photos/40/62/406286/landingpagemicrochippic32_sml.jpg)
PIC32MX440F512H-80V/MR
Manufacturer Part Number
PIC32MX440F512H-80V/MR
Description
512 KB Flash, 32 KB RAM, USB-OTG, 80 MHz, 10-Bit ADC, DMA 64 QFN 9x9x0.9mm TUBE
Manufacturer
Microchip Technology
Series
PIC® 32MXr
Datasheet
1.TDGL001.pdf
(214 pages)
Specifications of PIC32MX440F512H-80V/MR
Processor Series
PIC32MX4xx
Core
MIPS
Data Bus Width
32 bit
Program Memory Type
Flash
Program Memory Size
512 KB
Data Ram Size
32 KB
Interface Type
USB, I2C, UART, RS-232, RS-485, SPI
Maximum Clock Frequency
80 MHz
Number Of Programmable I/os
5
Number Of Timers
5
Operating Supply Voltage
2.3 V to 3.6 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Package / Case
QFN-64
Operating Temperature Range
- 40 C to + 105 C
Supply Current (max)
10 mA
Core Processor
MIPS32® M4K™
Core Size
32-Bit
Speed
80MHz
Connectivity
I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
53
Eeprom Size
-
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Lead Free Status / Rohs Status
Details
- Current page: 59 of 214
- Download datasheet (5Mb)
TABLE 4-10:
Legend:
Note
5000
5010 I2C1STAT
5020
5030
5040
5050
5260
5200
5210 I2C2STAT
5220
5230
5240
5250
5260
1:
I2C1CON
I2C1MSK
I2C1BRG
I2C2CON
I2C2MSK
I2C2BRG
I2C1ADD
I2C1TRN
I2C1RCV
I2C2ADD
I2C2TRN
I2C2RCV
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table except I2CxRCV have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See
Registers”
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
I2C1-2 REGISTERS MAP
for more information.
ACKSTAT
ACKSTAT
31/15
ON
ON
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRSTAT
TRSTAT
30/14
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
29/13
SIDL
SIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(1)
SCLREL
SCLREL
28/12
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
STRICT
STRICT
27/11
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
26/10
A10M
A10M
BCL
BCL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
GCSTAT
GCSTAT
DISSLW
DISSLW
25/9
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ADD10
ADD10
SMEN
SMEN
24/8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Bits
IWCOL
IWCOL
GCEN
GCEN
23/7
—
—
—
—
—
—
—
—
—
—
—
—
—
—
STREN
STREN
I2COV
I2COV
22/6
I2C1BRG<11:0>
I2C2BRG<11:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ACKDT
ACKDT
21/5
D/A
D/A
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ADD<9:0>
MSK<9:0>
ADD<9:0>
MSK<9:0>
ACKEN
ACKEN
I2CR1DATA<7:0>
I2CR2DATA<7:0>
I2CT1DATA<7:0>
I2CT2DATA<7:0>
20/4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
P
P
RCEN
RCEN
19/3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
S
S
Section 12.1.1 “CLR, SET and INV
18/2
PEN
PEN
R/W
R/W
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RSEN
RSEN
17/1
RBF
RBF
—
—
—
—
—
—
—
—
—
—
—
—
—
—
16/0
SEN
TBF
SEN
TBF
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
1000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
1000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
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