PIC32MX440F512H-80V/MR Microchip Technology, PIC32MX440F512H-80V/MR Datasheet - Page 39
![512 KB Flash, 32 KB RAM, USB-OTG, 80 MHz, 10-Bit ADC, DMA 64 QFN 9x9x0.9mm TUBE](/photos/40/62/406286/landingpagemicrochippic32_sml.jpg)
PIC32MX440F512H-80V/MR
Manufacturer Part Number
PIC32MX440F512H-80V/MR
Description
512 KB Flash, 32 KB RAM, USB-OTG, 80 MHz, 10-Bit ADC, DMA 64 QFN 9x9x0.9mm TUBE
Manufacturer
Microchip Technology
Series
PIC® 32MXr
Datasheet
1.TDGL001.pdf
(214 pages)
Specifications of PIC32MX440F512H-80V/MR
Processor Series
PIC32MX4xx
Core
MIPS
Data Bus Width
32 bit
Program Memory Type
Flash
Program Memory Size
512 KB
Data Ram Size
32 KB
Interface Type
USB, I2C, UART, RS-232, RS-485, SPI
Maximum Clock Frequency
80 MHz
Number Of Programmable I/os
5
Number Of Timers
5
Operating Supply Voltage
2.3 V to 3.6 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Package / Case
QFN-64
Operating Temperature Range
- 40 C to + 105 C
Supply Current (max)
10 mA
Core Processor
MIPS32® M4K™
Core Size
32-Bit
Speed
80MHz
Connectivity
I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
53
Eeprom Size
-
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Lead Free Status / Rohs Status
Details
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TABLE 3-1:
The MIPS architecture defines that the result of a mul-
tiply or divide operation be placed in the HI and LO reg-
isters. Using the Move-From-HI (MFHI) and Move-
From-LO (MFLO) instructions, these values can be
transferred to the general purpose register file.
In addition to the HI/LO targeted operations, the
MIPS32 architecture also defines a multiply instruction,
MUL, which places the least significant results in the
primary register file instead of the HI/LO register pair.
By avoiding the explicit MFLO instruction, required
when using the LO register, and by supporting multiple
destination
multiply-intensive operations is increased.
Two other instructions, multiply-add (MADD) and multi-
ply-subtract (MSUB), are used to perform the multiply-
accumulate and multiply-subtract operations. The
MADD instruction multiplies two numbers and then adds
TABLE 3-2:
© 2011 Microchip Technology Inc.
Register
Number
MULT/MULTU, MADD/MADDU,
0-6
10
11
12
12
12
12
13
14
15
15
16
16
16
16
7
8
9
MSUB/MSUBU
Register
Name
Reserved
HWREna
BadVAddr
Count
Reserved
Compare
Status
IntCtl
SRSCtl
SRSMap
Cause
EPC
PRId
EBASE
Config
Config1
Config2
Config3
DIV/DIVU
Opcode
registers,
MUL
(1)
(1)
(1)
MIPS
MULTIPLY/DIVIDE UNIT LATENCIES AND REPEAT RATES
COPROCESSOR 0 REGISTERS
(1)
(1)
(1)
(1)
(1)
(1)
®
M4K
the
®
PROCESSOR CORE HIGH-PERFORMANCE INTEGER
Function
Reserved
Enables access via the RDHWR instruction to selected hardware registers
Reports the address for the most recent address-related exception
Processor cycle count
Reserved
Timer interrupt control
Processor status and control
Interrupt system status and control
Shadow register set status and control
Provides mapping from vectored interrupt to a shadow set
Cause of last general exception
Program counter at last exception
Processor identification and revision
Exception vector base register
Configuration register
Configuration register 1
Configuration register 2
Configuration register 3
throughput
Operand Size (mul rt) (div rs)
of
16 bits
32 bits
16 bits
32 bits
16 bits
24 bits
32 bits
8 bits
the product to the current contents of the HI and LO
registers. Similarly, the MSUB instruction multiplies two
operands and then subtracts the product from the HI
and LO registers. The MADD and MSUB operations
are commonly used in DSP algorithms.
3.2.3
In the MIPS architecture, CP0 is responsible for the vir-
tual-to-physical address translation, the exception con-
trol system, the processor’s diagnostics capability, the
operating modes (kernel, user and debug), and
whether interrupts are enabled or disabled. Configura-
tion information, such as presence of options like
MIPS16e, is also available by accessing the CP0
registers, listed in
PIC32MX3XX/4XX
SYSTEM CONTROL
COPROCESSOR (CP0)
Table
Latency
12
19
26
33
1
2
2
3
3-2.
DS61143H-page 39
Repeat Rate
18
25
32
11
1
2
1
2
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