ICS1893CFLF IDT, Integrated Device Technology Inc, ICS1893CFLF Datasheet - Page 116
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ICS1893CFLF
Manufacturer Part Number
ICS1893CFLF
Description
PHYCEIVER LOW PWR 3.3V 48-SSOP
Manufacturer
IDT, Integrated Device Technology Inc
Series
PHYceiver™r
Type
PHY Transceiverr
Datasheet
1.ICS1893CFLFT.pdf
(127 pages)
Specifications of ICS1893CFLF
Protocol
MII
Voltage - Supply
3.14 V ~ 3.47 V
Mounting Type
Surface Mount
Package / Case
48-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Drivers/receivers
-
Lead Free Status / RoHS Status
Compliant, Lead free / RoHS Compliant
Other names
1893CFLF
800-1021
800-1021
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9.5.14 100M Media Independent Interface: Input-to-Carrier Assertion/De-Assertion
ICS1893CF, Rev. K, 05/13/10
TP_RX
CRS
COL
†
unscrambled.
Table 9-21
time periods consist of timings of signals on the following pins:
•
•
•
Figure 9-15
Table 9-21. 100M MDI Input-to-Carrier Assertion/De-Assertion Timing
† The IEEE maximum is 20 bit times.
‡ The IEEE minimum is 13 bit times, and the maximum is 24 bit times.
Figure 9-15. 100M MDI Input to Carrier Assertion / De-Assertion Timing Diagram
Shown
Period
†
Time
TP_RX (that is, TP_RXP and TP_RXN)
CRS
COL
t1
t2
t3
t4
ICS1893CF Data Sheet - Release
First Bit of /J/ into TP_RX to CRS Assert †
First Bit of /J/ into TP_RX while
Transmitting Data to COL Assert †
First Bit of /T/ into TP_RX to CRS
De-Assert ‡
First Bit of /T/ Received into TP_RX to
COL De-Assert ‡
lists the significant time periods for the 100M MDI input-to-carrier assertion/de-assertion. The
shows the timing diagram for the time periods.
First bit
t2
t1
Parameter
Copyright © 2009, Integrated Device Technology, Inc.
All rights reserved.
116
Half-Duplex Mode
Half-Duplex Mode
Conditions
–
–
Chapter 9 DC and AC Operating Conditions
First bit of /T/
t3
t4
Min.
10
13
13
9
Typ.
–
–
–
–
Max.
14
13
18
18
May, 2010
Bit times
Bit times
Bit times
Bit times
Units