ICS1893CFLF IDT, Integrated Device Technology Inc, ICS1893CFLF Datasheet - Page 115
![PHYCEIVER LOW PWR 3.3V 48-SSOP](/photos/6/88/68806/ics1893cflf_sml.jpg)
ICS1893CFLF
Manufacturer Part Number
ICS1893CFLF
Description
PHYCEIVER LOW PWR 3.3V 48-SSOP
Manufacturer
IDT, Integrated Device Technology Inc
Series
PHYceiver™r
Type
PHY Transceiverr
Datasheet
1.ICS1893CFLFT.pdf
(127 pages)
Specifications of ICS1893CFLF
Protocol
MII
Voltage - Supply
3.14 V ~ 3.47 V
Mounting Type
Surface Mount
Package / Case
48-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Drivers/receivers
-
Lead Free Status / RoHS Status
Compliant, Lead free / RoHS Compliant
Other names
1893CFLF
800-1021
800-1021
Available stocks
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Manufacturer
Quantity
Price
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Quantity:
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9.5.13 100M MII Media Independent Interface: Receive Latency
ICS1893CF, Rev. K, 05/13/10
TP_RX
RXCLK
RXD
Table 9-20
time periods consist of timings of signals on the following pins:
•
•
•
Figure 9-14
Table 9-20. 100M MII / 100M Stream Interface Receive Latency Timing
Figure 9-14. 100M MII / 100M Stream Interface: Receive Latency Timing Diagram
Period
†
unscrambled.
Time
TP_RX (that is, TP_RXP and TP_RXN)
RXCLK
RXD (that is, RXD[3:0])
Shown
t1
†
ICS1893CF Data Sheet Rev. J - Release
First Bit of /J/ into TP_RX to /J/ on RXD 100M MII
lists the significant time periods for the 100M MII / 100M Stream Interface receive latency. The
shows the timing diagram for the time periods.
Parameter
Copyright © 2009, Integrated Device Technology, Inc.
All rights reserved.
115
t1
Conditions
Chapter 9 DC and AC Operating Conditions
Min. Typ. Max.
–
16
17
Bit times
May, 2010
Units