PIC18F2455-I/SP Microchip Technology Inc., PIC18F2455-I/SP Datasheet - Page 28
PIC18F2455-I/SP
Manufacturer Part Number
PIC18F2455-I/SP
Description
Microcontroller; 24 KB Flash; 2048 RAM; 256 EEPROM; 24 I/O; 28-Pin-SPDIP
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC18F2455-ISP.pdf
(320 pages)
Specifications of PIC18F2455-I/SP
A/d Inputs
10-Channel, 10-Bit
Comparators
2
Cpu Speed
12 MIPS
Eeprom Memory
256 Bytes
Input Output
23
Interface
I2C/SPI/USART/USB
Memory Type
Flash
Number Of Bits
8
Package Type
28-pin SPDIP
Programmable Memory
24K Bytes
Ram Size
2K Bytes
Speed
48 MHz
Timers
1-8-bit, 3-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F2455-I/SP
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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- Download datasheet (6Mb)
PIC18F2450/4450
FIGURE 2-3:
2.2.3
The EC, ECIO, ECPLL and ECPIO Oscillator modes
require an external clock source to be connected to the
OSC1 pin. There is no oscillator start-up time required
after a Power-on Reset or after an exit from Sleep
mode.
In the EC and ECPLL Oscillator modes, the oscillator
frequency divided by 4 is available on the OSC2 pin.
This signal may be used for test purposes or to
synchronize other logic. Figure 2-4 shows the pin
connections for the EC Oscillator mode.
FIGURE 2-4:
The ECIO and ECPIO Oscillator modes function like the
EC and ECPLL modes, except that the OSC2 pin
becomes an additional general purpose I/O pin. The I/O
pin becomes bit 6 of PORTA (RA6). Figure 2-5 shows
the pin connections for the ECIO Oscillator mode.
FIGURE 2-5:
The internal postscaler for reducing clock frequency in
XT and HS modes is also available in EC and ECIO
modes.
DS39760A-page 26
Clock from
Ext. System
Clock from
Ext. System
Clock from
Ext. System
EXTERNAL CLOCK INPUT
F
Open
OSC
RA6
/4
EXTERNAL CLOCK INPUT
OPERATION (HS OSC
CONFIGURATION)
EXTERNAL CLOCK
INPUT OPERATION
(EC AND ECPLL
CONFIGURATION)
EXTERNAL CLOCK
INPUT OPERATION
(ECIO AND ECPIO
CONFIGURATION)
OSC1
OSC2
OSC1/CLKI
OSC2/CLKO
OSC1/CLKI
I/O (OSC2)
PIC18FXXXX
PIC18FXXXX
PIC18FXXXX
(HS Mode)
Advance Information
2.2.4
PIC18F2450/4450 devices include a Phase Locked
Loop (PLL) circuit. This is provided specifically for USB
applications with lower speed oscillators and can also
be used as a microcontroller clock source.
The PLL is enabled in HSPLL, XTPLL, ECPLL and
ECPIO Oscillator modes. It is designed to produce a
fixed 96 MHz reference clock from a fixed 4 MHz input.
The output can then be divided and used for both the
USB and the microcontroller core clock. Because the
PLL has a fixed frequency input and output, there are
eight prescaling options to match the oscillator input
frequency to the PLL.
There is also a separate postscaler option for deriving
the microcontroller clock from the PLL. This allows the
USB peripheral and microcontroller to use the same
oscillator input and still operate at different clock
speeds. In contrast to the postscaler for XT, HS and EC
modes, the available options are 1/2, 1/3, 1/4 and 1/6
of the PLL output.
The HSPLL, ECPLL and ECPIO modes make use of
the HS mode oscillator for frequencies up to 48 MHz.
The prescaler divides the oscillator input by up to 12 to
produce the 4 MHz drive for the PLL. The XTPLL mode
can only use an input frequency of 4 MHz which drives
the PLL directly.
FIGURE 2-6:
HS/EC/ECIO/XT Oscillator Enable
OSC2
OSC1
(from CONFIG1H Register)
Oscillator
Prescaler
PLL FREQUENCY MULTIPLIER
and
F
F
PLL Enable
PLL BLOCK DIAGRAM
(HS MODE)
IN
OUT
24
© 2006 Microchip Technology Inc.
Comparator
Phase
Loop
Filter
VCO
SYSCLK
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