DS1642-100+ Dallas Semiconductor, DS1642-100+ Datasheet - Page 3
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DS1642-100+
Manufacturer Part Number
DS1642-100+
Description
Real Time Clock (RTC), 2KB x 8 Nonvolatile SRAM, EDIP28
Manufacturer
Dallas Semiconductor
Datasheet
1.DS1642-100.pdf
(12 pages)
Specifications of DS1642-100+
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
CLOCK OPERATIONS–READING THE CLOCK
While the double-buffered register structure reduces the chance of reading incorrect data, internal updates
to the DS1642 clock registers should be halted before clock data is read to prevent reading of data in
transition. However, halting the internal clock register updating process does not affect clock accuracy.
Updating is halted when a 1 is written into the read bit, the 7th most significant bit in the control register.
As long as a 1 remains in that position, updating is halted. After a halt is issued, the registers reflect the
count, that is day, date, and time that was current at the moment the halt command was issued. However,
the internal clock registers of the double-buffered system continue to update so that the clock accuracy is
not affected by the access of data. All of the DS1642 registers are updated simultaneously after the clock
status is reset. Updating occurs within a second after the read bit is written to 0.
Figure 1. DS1642 BLOCK DIAGRAM
Table 1. TRUTH TABLE
<4.5V > V
5V ±10%
<V
V
CC
BAT
BAT
V
V
V
V
CE
X
X
IH
IL
IL
IL
V
V
OE
X
X
X
X
IH
IL
WE
V
V
V
X
X
X
IH
IH
IL
Deselect
Deselect
Deselect
3 of 12
MODE
Write
Read
Read
Data Out
High-Z
Data In
High-Z
High-Z
High-Z
DQ
Data Retention Mode
CMOS Standby
POWER
Standby
Active
Active
Active