FWIXP420BD Intel, FWIXP420BD Datasheet - Page 35
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FWIXP420BD
Manufacturer Part Number
FWIXP420BD
Description
IC NETWRK PROCESSR 533MHZ 492BGA
Manufacturer
Intel
Specifications of FWIXP420BD
Processor Type
Network
Features
XScale Core
Speed
533MHz
Voltage
1.3V
Mounting Type
Surface Mount
Package / Case
492-BGA
Core Operating Frequency
533MHz
Package Type
BGA
Pin Count
492
Mounting
Surface Mount
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
860130
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
FWIXP420BD
Manufacturer:
AMD
Quantity:
55
Datasheet
Table 8.
Table 9.
High-Speed, Serial Interface 1
MII Interfaces (Sheet 1 of 2)
HSS_TXFRAME1
HSS_TXDATA1
HSS_TXCLK1
HSS_RXFRAME1
HSS_RXDATA1
HSS_RXCLK1
†
ETH_TXCLK0
ETH_TXDATA0[3:0]
ETH_TXEN0
ETH_RXCLK0
†
For a legend of the Type codes, see
For a legend of the Type codes, see
Name
Name
Reset
Power
On
Power
Reset
Z
Z
Z
Z
Z
Z
On
Z
Z
Z
Z
Intel
†
†
Reset
®
Reset
VI
Z
Z
Z
Z
Z
IXP42X Product Line and IXC1100 Control Plane Processor
VI
VI
0
0
Table 4 on page
Table 4 on page
†
†
Type
O/D
I/O
I/O
I/O
I/O
Type
I
O
O
I
I
†
†
The High-Speed Serial (HSS) transmit frame signal can be configured as
an input or an output to allow an external source to be synchronized with
the transmitted data. Often known as a Frame Sync signal. Configured as
an input upon reset.
Should be pulled low with a 10-KΩ resistor when not being utilized in the
system.
Transmit data out. Open Drain output.
Must be pulled high with a 10-KΩ resistor to V
The High-Speed Serial (HSS) transmit clock signal can be configured as
an input or an output. The clock can be a frequency ranging from 512 KHz
to 8.192 MHz. Used to clock out the transmitted data. Configured as an
input upon reset. Frame sync and Data can be selected to be generated
on the rising or falling edge of the transmit clock.
Should be pulled low with a 10-KΩ resistor when not being utilized in the
system.
The High-Speed Serial (HSS) receive frame signal can be configured as
an input or an output to allow an external source to be synchronized with
the received data. Often known as a Frame Sync signal. Configured as an
input upon reset.
Should be pulled low with a 10-KΩ resistor when not being utilized in the
system.
Receive data input. Can be sampled on the rising or falling edge of the
receive clock.
Should be pulled low through a 10-KΩ resistor when not being utilized in
the system.
The High-Speed Serial (HSS) receive clock signal can be configured as
an input or an output. The clock can be from 512 KHz to 8.192 MHz. Used
to sample the received data. Configured as an input upon reset.
Should be pulled low with a 10-KΩ resistor when not being utilized in the
system.
30.
30.
Externally supplied transmit clock.
Should be pulled low through a 10-KΩ resistor when not being utilized in
the system.
Transmit data bus to PHY, asserted synchronously with respect to
ETH_TXCLK0.
Indicates that the PHY is being presented with nibbles on the MII
interface. Asserted synchronously, with respect to ETH_TXCLK0, at the
first nibble of the preamble and remains asserted until all the nibbles of a
frame are presented.
Externally supplied receive clock.
Should be pulled low through a 10-KΩ resistor when not being utilized in
the system.
•
•
•
•
25 MHz for 100-Mbps operation
2.5 MHz for 10 Mbps
25 MHz for 100-Mbps operation
2.5 MHz for 10 Mbps
Functional Signal Descriptions
Description
Description
CCP
.
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