PNX1502E/G,557 NXP Semiconductors, PNX1502E/G,557 Datasheet - Page 486
PNX1502E/G,557
Manufacturer Part Number
PNX1502E/G,557
Description
IC MEDIA PROC 300MHZ 456-BGA
Manufacturer
NXP Semiconductors
Specifications of PNX1502E/G,557
Applications
Multimedia
Core Processor
TriMedia
Controller Series
Nexperia
Interface
I²C, 2-Wire Serial
Number Of I /o
61
Voltage - Supply
1.23 V ~ 1.37 V
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
456-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Program Memory Type
-
Ram Size
-
Lead Free Status / Rohs Status
Compliant
Other names
568-1298
935277748557
PNX1502E/G
935277748557
PNX1502E/G
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Philips Semiconductors
Volume 1 of 1
PNX15XX_SER_3
Product data sheet
Figure 2:
fgpi_d_valid
fgpi_data
fgpi_start
fgpi_stop
FGPI Module Block Diagram
8/16/32
DTL
MMIO
I/F
1.2 VDI to FGPI pin mapping
1.3 DTL MMIO Interface
1.4 Data Packer
Refer to
VDI_D[32] maps to fgpi_start (fgpi_rec_start)
VDI_D[33] maps to fgpi_stop (fgpi_buf_start)
VDI_V2 maps to fgpi_d_valid
VDI_C2 maps to clock module fgpi_clk input
VDI_D[31:0] mapping depends on the VDI_MODE (Input Router) register settings as
described in the
This block contains all of the programmable registers used by the FGPI module
accessed through the MMIO bus. Refer to
descriptions. This block also handles clock domain crossing between the MMIO bus
clock and the FGPI module clock.
This block is used to pack incoming data samples into 32-bit words to be sent to main
memory. This module also informs the DMA Engine when a valid 32-bit data word is
ready to be loaded into the MTL DTL adapters FIFO via the DTL Initiators.
DATA
PACKER
BUFFER
SYNC
Figure
2. This block diagram shows the basic sections of the FGPI module.
Chapter 3 System On Chip
Rev. 3 — 17 March 2006
32
TIMESTAMP
LENGTH
DMA
ENGINE
Chapter 14: FGPI: Fast General Purpose Interface
32
32
Section 4. on page 14-18
Resources.
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
DTL
INITIATOR
DTL
INITIATOR
PNX15xx Series
for register
14-3
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