XC5VFX30T-1FFG665CES Xilinx Inc, XC5VFX30T-1FFG665CES Datasheet - Page 41
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XC5VFX30T-1FFG665CES
Manufacturer Part Number
XC5VFX30T-1FFG665CES
Description
IC FPGA VIRTEX5FX 30K 665FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 FXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VFX30T-1FFG665CES
Number Of Logic Elements/cells
32768
Number Of Labs/clbs
2560
Total Ram Bits
2506752
Number Of I /o
360
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
665-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS non-compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VFX30T-1FFG665CES
Manufacturer:
Xilinx Inc
Quantity:
10 000
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Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
I/O Clock Buffer - BUFIO
BUFIO Primitive
BUFIO Use Models
The I/O clock buffer (BUFIO) is a clock buffer available in Virtex-5 devices. The BUFIO
drives a dedicated clock net within the I/O column, independent of the global clock
resources. Thus, BUFIOs are ideally suited for source-synchronous data capture
(forwarded/receiver clock distribution). BUFIOs can only be driven by clock capable I/Os
located in the same clock region. In a typical clock region, there are four BUFIOs. Each
BUFIO can drive a single I/O clock network in the same region/bank, as well as the
regional clock buffers (BUFR). BUFIOs cannot drive logic resources (CLB, block RAM,
IODELAY, etc.) because the I/O clock network only reaches the I/O column in the same
bank or clock region.
BUFIO is simply a clock in, clock out buffer. There is a phase delay between input and
output.
is available for BUFIO.
X-Ref Target - Figure 1-18
Table 1-6: BUFIO Port List and Definitions
In
implementation is ideal in source-synchronous applications where a forwarded clock is
used to capture incoming data.
O
I
Port Name
Figure
Figure 1-18
1-19, a BUFIO is used to drive the I/O logic using the clock capable I/O. This
Output
Input
shows the BUFIO.
Type
www.xilinx.com
Figure 1-18: BUFIO Primitive
I
1
1
Table 1-6
Width
BUFIO
ug190_1_18_032306
lists the BUFIO ports. A location constraint
Clock output port
Clock input port
O
Regional Clocking Resources
Definition
41
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