XC5VFX30T-1FFG665CES Xilinx Inc, XC5VFX30T-1FFG665CES Datasheet - Page 330
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XC5VFX30T-1FFG665CES
Manufacturer Part Number
XC5VFX30T-1FFG665CES
Description
IC FPGA VIRTEX5FX 30K 665FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 FXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VFX30T-1FFG665CES
Number Of Logic Elements/cells
32768
Number Of Labs/clbs
2560
Total Ram Bits
2506752
Number Of I /o
360
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
665-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS non-compliant
Number Of Gates
-
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Company:
Part Number:
XC5VFX30T-1FFG665CES
Manufacturer:
Xilinx Inc
Quantity:
10 000
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Chapter 7: SelectIO Logic Resources
330
IODELAY Timing
ODELAY_VALUE Attribute
The ODELAY_VALUE attribute specifies tap delays. The possible values are any integer
from 0 to 63. The default value is zero. The value of the tap delay reverts to
ODELAY_VALUE when the tap delay is reset.
HIGH_PERFORMANCE_MODE Attribute
When TRUE, this attribute reduces the output jitter. This reduction results in a slight
increase in power dissipation from the IODELAY element. When set to FALSE the
IODELAY element consumes less power.
SIGNAL_PATTERN Attribute
Clock and data signals have different electrical profiles and therefore accumulate different
amounts of jitter in the IODELAY chain. By setting the SIGNAL_PATTERN attribute, the
user enables timing analyzer to account for jitter appropriately when calculating timing. A
clock signal is periodic in nature and does not have long sequences of consecutive ones or
zeroes, while data is random in nature and can have long and short sequences of ones and
zeroes.
Table 7-11
Table 7-11: IODELAY Switching Characteristics
Figure 7-9
X-Ref Target - Figure 7-9
T
T
T
T
IDELAYRESOLUTION
ICECK
IINCCK
IRSTCK
DATAOUT
/T
/T
/T
RST
INC
CE
shows the IODELAY switching characteristics.
ICKCE
shows an IDELAY timing diagram. It is assumed that IDELAY_VALUE = 0.
ICKINC
ICKRST
C
Symbol
Figure 7-9: IDELAY Timing Diagram
www.xilinx.com
1
Tap 0
IDELAY tap resolution
CE pin Setup/Hold with respect to C
INC pin Setup/Hold with respect to C
RST pin Setup/Hold with respect to C
2
3
Tap 1
Description
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
UG190_7_09_100107
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