XC5VFX30T-1FFG665CES Xilinx Inc, XC5VFX30T-1FFG665CES Datasheet - Page 305
![IC FPGA VIRTEX5FX 30K 665FCBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VFX30T-1FFG665CES
Manufacturer Part Number
XC5VFX30T-1FFG665CES
Description
IC FPGA VIRTEX5FX 30K 665FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 FXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VFX30T-1FFG665CES
Number Of Logic Elements/cells
32768
Number Of Labs/clbs
2560
Total Ram Bits
2506752
Number Of I /o
360
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
665-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS non-compliant
Number Of Gates
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VFX30T-1FFG665CES
Manufacturer:
Xilinx Inc
Quantity:
10 000
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Simultaneous Switching Output Limits
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Sparse-Chevron Packages
When multiple output drivers change state at the same time, power supply disturbance
occurs. These disturbances can cause undesired transient behavior in output drivers, input
receivers, or in internal logic. These disturbances are often referred to as Simultaneous-
Switching Output (SSO) noise. The SSO limits govern the number and type of I/O output
drivers that can be switched simultaneously while maintaining a safe level of SSO noise.
Virtex-5 FPGA packaging utilizes a sparse-chevron pinout arrangement. The sparse-
chevron pinout style is an improvement over previous designs, offering low crosstalk and
SSO noise. The pinout is designed to minimize PDS inductance and keep I/O signal return
current paths very closely coupled to their associated I/O signal.
The maximum ratio of I/O to reference pins (V
is 4:1. For every four I/O pins, there is always at least one reference pin.
For boards that do not meet the nominal PCB requirements listed in
Specifications, the Virtex-5 FPGA SSO calculator is available, containing all SSO limit data
for all I/O standards. For designs in nominal PCBs mixing limited and “no limit” I/O
standards, the Virtex-5 FPGA SSO calculator must be used to ensure that I/O utilization
does not exceed the limit. Information on the calculator is available under the
SSO Calculator
Unlike devices in previous families, Virtex-5 devices have only two bank sizes: 20 I/O and
40 I/O. With the ratio of signal to reference pins always constant, the SSO capacity of all
banks of 20 I/O are the same, and the capacity of all banks of 40 I/O are the same. The SSO
limits for Virtex-5 devices are listed on a per-bank basis rather than a limit per V
pair.
section.
www.xilinx.com
CCO
Simultaneous Switching Output Limits
and GND) in sparse-chevron packages
Nominal PCB
Full Device
CCO
/GND
305
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