XC5VFX30T-1FFG665CES Xilinx Inc, XC5VFX30T-1FFG665CES Datasheet - Page 28
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XC5VFX30T-1FFG665CES
Manufacturer Part Number
XC5VFX30T-1FFG665CES
Description
IC FPGA VIRTEX5FX 30K 665FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 FXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VFX30T-1FFG665CES
Number Of Logic Elements/cells
32768
Number Of Labs/clbs
2560
Total Ram Bits
2506752
Number Of I /o
360
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
665-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS non-compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VFX30T-1FFG665CES
Manufacturer:
Xilinx Inc
Quantity:
10 000
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Chapter 1: Clock Resources
28
Global Clock Buffer Primitives
The primitives in
Table 1-2: Global Clock Buffer Primitives
BUFGCTRL
The BUFGCTRL primitive shown in
clocks. All other global clock buffer primitives are derived from certain configurations of
BUFGCTRL. The ISE® software tools manage the configuration of all these primitives.
BUFGCTRL has four select lines, S0, S1, CE0, and CE1. It also has two additional control
lines, IGNORE0 and IGNORE1. These six control lines are used to control the input I0 and
I1.
X-Ref Target - Figure 1-1
Notes:
1. All primitives are derived from a software preset of BUFGCTRL.
2. This primitive replaces the BUFGMUX_VIRTEX4 primitive.
BUFGCTRL
BUFG
BUFGCE
BUFGCE_1
BUFGMUX
BUFGMUX_1
BUFGMUX_CTRL
Primitive
(1)
Table 1-2
(2)
www.xilinx.com
Figure 1-1: BUFGCTRL Primitive
are different configurations of the global clock buffers.
Input
I0, I1
I0, I1
I0, I1
I0, I1
I
I
I
IGNORE1
CE1
S1
I1
I0
S0
CE0
IGNORE0
Figure
Output
BUFGCTRL
O
O
O
O
O
O
O
ug190_1_01_032206
1-1, can switch between two asynchronous
CE0, CE1, IGNORE0, IGNORE1, S0, S1
–
CE
CE
S
S
S
O
Control
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
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