XC5VFX30T-1FFG665CES Xilinx Inc, XC5VFX30T-1FFG665CES Datasheet - Page 218
![IC FPGA VIRTEX5FX 30K 665FCBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VFX30T-1FFG665CES
Manufacturer Part Number
XC5VFX30T-1FFG665CES
Description
IC FPGA VIRTEX5FX 30K 665FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 FXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VFX30T-1FFG665CES
Number Of Logic Elements/cells
32768
Number Of Labs/clbs
2560
Total Ram Bits
2506752
Number Of I /o
360
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
665-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS non-compliant
Number Of Gates
-
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Chapter 6: SelectIO Resources
SelectIO Resources Introduction
SelectIO Resources General Guidelines
218
Virtex-5 FPGA I/O Bank Rules
All Virtex-5 FPGAs have configurable high-performance SelectIO™ drivers and receivers,
supporting a wide variety of standard interfaces. The robust feature set includes
programmable control of output strength and slew rate, and on-chip termination using
Digitally Controlled Impedance (DCI).
Each IOB contains both input, output, and 3-state SelectIO drivers. These drivers can be
configured to various I/O standards. Differential I/O uses the two IOBs grouped together
in one tile.
•
•
•
Each Virtex-5 FPGA I/O tile contains two IOBs, and also two ILOGIC blocks and two
OLOGIC blocks, as described in
Figure 6-2
X-Ref Target - Figure 6-2
Each IOB has a direct connection to an ILOGIC/OLOGIC pair containing the input and
output logic resources for data and 3-state control for the IOB. Both ILOGIC and OLOGIC
can be configured as ISERDES and OSERDES, respectively, as described in
Advanced SelectIO Logic
This section summarizes the general guidelines to be considered when designing with the
SelectIO resources in Virtex-5 FPGAs.
In Virtex-5 devices, with some exceptions in the center column, an I/O bank consists of 40
IOBs (20 CLBs high and a single clock region). There are always four half-sized banks
(20 IOBs) and a single configuration bank in the center column. The number of banks
DIFFI_IN
Single-ended I/O standards (LVCMOS, LVTTL, HSTL, SSTL, GTL, PCI)
Differential I/O standards (LVDS, HT, LVPECL, BLVDS, Differential HSTL and SSTL)
Differential and V
O
T
shows the basic IOB and its connections to the internal logic and the device Pad.
REF
www.xilinx.com
Resources.
dependent inputs are powered by V
Figure 6-2: Basic IOB Diagram
Chapter 7, SelectIO Logic
OUTBUF
PAD
INBUF
Resources.
CCAUX
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
DIFFO_IN
Chapter 8,
ug190_6_02_021306
PADOUT
DIFFO_OUT
I
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