XCV1600E-6FG860C Xilinx Inc, XCV1600E-6FG860C Datasheet - Page 34
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XCV1600E-6FG860C
Manufacturer Part Number
XCV1600E-6FG860C
Description
IC FPGA 1.8V C-TEMP 860-FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-Er
Datasheet
1.XCV200E-6CS144C.pdf
(233 pages)
Specifications of XCV1600E-6FG860C
Number Of Logic Elements/cells
34992
Number Of Labs/clbs
7776
Total Ram Bits
589824
Number Of I /o
660
Number Of Gates
2188742
Voltage - Supply
1.71 V ~ 1.89 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
860-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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Virtex™-E 1.8 V Field Programmable Gate Arrays
At the third rising edge of CLKA, the T
violated with two writes to memory location 0x0F. The DOA
and DOB buses reflect the contents of the DIA and DIB
buses, but the stored value at 0x0F is invalid.
At the fourth rising edge of CLKA, a read operation is per-
formed at memory location 0x0F and invalid data is present
on the DOA bus. Port B also executes a read operation to
memory location 0x0F and also reads invalid data.
At the fifth rising edge of CLKA a read operation is per-
formed that does not violate the T
previous write of 0x7E by Port B. THe DOA bus reflects the
recently written value by Port B.
Initialization
The block SelectRAM+ memory can initialize during the
device configuration sequence. The 16 initialization properties
of 64 hex values each (a total of 4096 bits) set the initialization
of each RAM. These properties appear in
ization properties not explicitly set configure as zeros. Partial
initialization strings pad with zeros. Initialization strings
greater than 64 hex values generate an error. The RAMs can
be simulated with the initialization values using generics in
VHDL simulators and parameters in Verilog simulators.
Initialization in VHDL and Synopsys
The block SelectRAM+ structures can be initialized in VHDL
for both simulation and synthesis for inclusion in the EDIF
output file. The simulation of the VHDL code uses a generic
to pass the initialization. Synopsys FPGA compiler does not
Module 2 of 4
28
Figure 34: Timing Diagram for a True Dual-port Read/Write Block SelectRAM+ Memory
ADDR_A
ADDR_B
CLK_A
CLK_B
WE_A
WE_B
DO_A
DO_B
EN_A
EN_B
DI_A
DI_B
1111
00
MEM (00)
AAAA
BCCS
00
T
BCCS
Table
BCCS
1111
parameter to the
00
AAAA
17. Any initial-
parameter is
AAAA
9999
VIOLATION
7E
1111
T
7E
BCCS
www.xilinx.com
9999
9999
BBBB
presently support generics. The initialization values instead
attach as attributes to the RAM by a built-in Synopsys
dc_script. The translate_off statement stops synthesis
translation of the generic statements. The following code
illustrates a module that employs these techniques.
Table 17: RAM Initialization Properties
AAAA
0F
0F
BBBB
AAAA
1111
Property
0F
INIT_00
INIT_01
INIT_02
INIT_03
INIT_04
INIT_05
INIT_06
INIT_07
INIT_08
INIT_09
INIT_0a
INIT_0b
INIT_0c
INIT_0d
INIT_0e
INIT_0f
UNKNOWN
0000
0F
T
BCCS
UNKNOWN
2222
7E
2222
Production Product Specification
1111
7E
DS022-2 (v2.8) January 16, 2006
ds022_035_121399
FFFF
2222
1A
FFFF
Memory Cells
1279 to 1024
1535 to 1280
1791 to 2047
2047 to 1792
2303 to 2048
2559 to 2304
2815 to 2560
3071 to 2816
3327 to 3072
3583 to 3328
3839 to 3584
4095 to 3840
1023 to 768
511 to 256
767 to 512
255 to 0
R
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