AT40K20LV-3AJC Atmel, AT40K20LV-3AJC Datasheet - Page 11
AT40K20LV-3AJC
Manufacturer Part Number
AT40K20LV-3AJC
Description
IC FPGA 3.3V 1024 CELL 84-PLCC
Manufacturer
Atmel
Series
AT40K/KLVr
Datasheet
1.AT40K05-2BQC.pdf
(67 pages)
Specifications of AT40K20LV-3AJC
Number Of Logic Elements/cells
1024
Total Ram Bits
8192
Number Of I /o
62
Number Of Gates
30000
Voltage - Supply
3 V ~ 3.6 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 70°C
Package / Case
84-PLCC
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Labs/clbs
-
- Current page: 11 of 67
- Download datasheet (2Mb)
RAM
0896C–FPGA–04/02
32 x 4 dual-ported RAM blocks are dispersed throughout the array, see Figure 7. A 4-bit
Input Data Bus connects to four horizontal local buses distributed over four sector rows
(plane 1). A 4-bit Output Data Bus connects to four horizontal local buses distributed
over four sectors in the same column. A 5-bit Output Address Bus connects to five verti-
cal express buses in the same column. Ain (input address) and Aout (output address)
alternate positions in horizontally aligned RAM blocks. For the left-most RAM blocks,
Aout is on the left and Ain is on the right. For the right-most RAM blocks, Ain is on the
left and Aout is tied off, thus it can only be configured as a single port. For single-ported
RAM, Ain is the READ/WRITE address port and Din is the (bi-directional) data port.
Right-most RAM blocks can be used only for single-ported memories. WEN and OEN
connect to the vertical express buses in the same column.
Figure 7. RAM Connections (One Ram Block)
AT40K/AT40KLV Series FPGA
CLK
CLK
CLK
CLK
Ain
WEN
OEN
32 x 4 RAM
Din
CLK
Dout
Aout
11
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