XC4VFX12-12FFG668C Xilinx Inc, XC4VFX12-12FFG668C Datasheet - Page 67
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XC4VFX12-12FFG668C
Manufacturer Part Number
XC4VFX12-12FFG668C
Description
IC FPGA VIRTEX-4 FX 12K 668FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r
Specifications of XC4VFX12-12FFG668C
Number Of Logic Elements/cells
12312
Number Of Labs/clbs
1368
Total Ram Bits
663552
Number Of I /o
320
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
668-BBGA, FCBGA
For Use With
HW-V4-ML403-UNI-G - EVALUATION PLATFORM VIRTEX-4HW-AFX-FF668-400 - BOARD DEV VIRTEX 4 FF668
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
CLKDV_DIVIDE Attribute
CLKFX_MULTIPLY and CLKFX_DIVIDE Attributes
CLKIN_DIVIDE_BY_2 Attribute
CLKIN_PERIOD Attribute
R
The CLKDV_DIVIDE attribute controls the CLKDV frequency. The source clock frequency
is divided by the value of this attribute. The possible values for CLKDV_DIVIDE are: 1.5,
2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6, 6.5, 7, 7.5, 8, 9, 10, 11, 12, 13, 14, 15, or 16. The default value is 2.
In the low frequency mode, any CLKDV_DIVIDE value produces a CLKDV output with a
50/50 duty-cycle. In the high frequency mode, the CLKDV_DIVIDE value must be set to
an integer value to produce a CLKDV output with a 50/50 duty-cycle. For non-integer
CLKDV_DIVIDE values, the CLKDV output duty cycle is shown in
Table 2-7: Non-Integer CLKDV_DIVIDE
The CLKFX_MULTIPLY attribute sets the multiply value (M) of the CLKFX output. The
CLKFX_DIVIDE attribute sets the divisor (D) value of the CLKFX output. Both control the
CLKFX output making the CLKFX frequency equal the effective CLKIN (source clock)
frequency multiplied by M/D. The possible values for M are any integer from 2 to 32. The
possible values for D are any integer from 1 to 32. The default settings are M = 4 and D = 1.
The CLKIN_DIVIDE_BY_2 attribute is used to enable a toggle flip-flop in the input clock
path to the DCM. When set to FALSE, the effective CLKIN frequency of the DCM equals
the source clock frequency driving the CLKIN input. When set to TRUE, the CLKIN
frequency is divided by two before it reaches the rest of the DCM. Thus, the DCM sees half
the frequency applied to the CLKIN input and operates based on this frequency. For
example, if a 100 MHz clock drives CLKIN, and CLKIN_DIVIDE_BY_2 is set to TRUE;
then the effective CLKIN frequency is 50 MHz. Thus, CLK0 output is 50 MHz and CLK2X
output is 100 MHz. The effective CLKIN frequency must be used to evaluate any operation
or specification derived from CLKIN frequency. The possible values for
CLKIN_DIVIDE_BY_2 are TRUE and FALSE. The default value is FALSE.
The CLKIN_PERIOD attribute specifies the source clock period (in nanoseconds). The
default value is 0.0 ns.
CLKDV_DIVIDE Value
1.5
2.5
3.5
4.5
5.5
6.5
7.5
www.xilinx.com
(High Pulse/Low Pulse Value)
High Frequency Mode
CLKDV Duty Cycle in
5/11
6/13
7/15
1/3
2/5
3/7
4/9
Table
DCM Attributes
2-7.
67
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