XC4VFX12-12FFG668C Xilinx Inc, XC4VFX12-12FFG668C Datasheet - Page 23
![no-image](/images/no-image-200.jpg)
XC4VFX12-12FFG668C
Manufacturer Part Number
XC4VFX12-12FFG668C
Description
IC FPGA VIRTEX-4 FX 12K 668FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r
Specifications of XC4VFX12-12FFG668C
Number Of Logic Elements/cells
12312
Number Of Labs/clbs
1368
Total Ram Bits
663552
Number Of I /o
320
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
668-BBGA, FCBGA
For Use With
HW-V4-ML403-UNI-G - EVALUATION PLATFORM VIRTEX-4HW-AFX-FF668-400 - BOARD DEV VIRTEX 4 FF668
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC4VFX12-12FFG668C
Manufacturer:
XILINX
Quantity:
185
Company:
Part Number:
XC4VFX12-12FFG668C
Manufacturer:
Xilinx Inc
Quantity:
10 000
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Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
Online Document
R
The following conventions are used in this document:
Italic font
Square brackets [ ]
Braces { }
Vertical bar |
Vertical ellipsis
.
.
.
Horizontal ellipsis . . .
Blue text
Red text
Blue, underlined text
Convention
Convention
Variables in a syntax statement
for which you must supply
values
References to other manuals
Emphasis in text
An optional entry or parameter.
However, in bus specifications,
such as bus[7:0], they are
required.
A list of items from which you
must choose one or more
Separates items in a list of
choices
Repetitive material that has
been omitted
Repetitive material that has
been omitted
Cross-reference link to a location
in the current document
Cross-reference link to a location
in another document
Hyperlink to a website (URL)
www.xilinx.com
Meaning or Use
Meaning or Use
ngdbuild design_name
See the Development System
Reference Guide for more
information.
If a wire is drawn so that it
overlaps the pin of a symbol, the
two nets are not connected.
ngdbuild [option_name]
design_name
lowpwr ={on|off}
lowpwr ={on|off}
IOB #1: Name = QOUT’
IOB #2: Name = CLKIN’
.
.
.
allow block block_name loc1
loc2 ... locn;
See the section
Resources”
Refer to
Chapter 1
See
Platform FPGA User Guide.
Go to
for the latest speed files.
Figure 5
http://www.xilinx.com
“Title Formats” in
for details.
Example
Example
for details.
in the Virtex-II
“Additional
Conventions
23
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