XC2VP7-5FFG672I Xilinx Inc, XC2VP7-5FFG672I Datasheet - Page 20
Manufacturer Part Number
IC FPGA VIRTEX-II PRO 672-FBGA
Specifications of XC2VP7-5FFG672I
Number Of Logic Elements/cells
Number Of Labs/clbs
Total Ram Bits
Number Of I /o
Voltage - Supply
1.425 V ~ 1.575 V
-40°C ~ 100°C
Package / Case
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
Other RocketIO X Features and Notes
In order to facilitate testing without having the need to either
apply patterns or measure data at GHz rates, four program-
mable loop-back features are available.
The first option, serial loopback, is available in two modes:
pre-driver and post-driver.
The third option, parallel loopback, checks the digital cir-
cuitry. When parallel loopback is enabled, the serial loop-
back path is disabled. However, the transmitter outputs
remain active, and data can be transmitted. If TXINHIBIT is
asserted, TXP is forced to 0 until TXINHIBIT is de-asserted.
The fourth option, repeater loopback, allows received data
to be transmitted without going through the FPGA fabric.
The receiver and transmitter have their own synchronous
reset inputs. The transmitter reset, TXRESET, recenters the
transmission FIFO and resets all transmitter registers and
the encoder. The receiver reset, RXRESET, recenters the
DS083 (v4.7) November 5, 2007
The pre-driver mode loops back to the receiver without
going through the output driver. In this mode, TXP and
TXN are not driven and therefore need not be
The post-driver mode is the same as the RocketIO
loopback. In this mode, TXP and TXN are driven and
must be properly terminated.
Virtex-II Pro and Virtex-II Pro X Platform FPGAs: Functional Description
receiver elastic buffer and resets all receiver registers and
the decoder. When the signals TXRESET or RXRESET are
asserted High, the PCS is in reset. After TXRESET or
RXRESET are deasserted, the PCS takes five clocks to
come out of reset for each clock domain.
The PMA configuration vector is not affected during this
reset, so the PMA speed, filter settings, and so on, all
remain the same. Also, the PMA internal pipeline is not
affected and continues to operate in normal fashion.
The transceiver voltage regulator circuits must not be
shared with any other supplies (including FPGA supplies
be shared among transceiver power supplies of the same
voltage, but each supply pin must still have its own separate
passive filtering network.
All RocketIO transceivers in the FPGA, whether instantiated
in the design or not, must be connected to power and
ground. Unused transceivers can be powered by any 1.5V
or 2.5V source, and passive filtering is not required.
The Power Down feature is controlled by the transceiver’s
POWERDOWN input pin. Any given transceiver that is not
instantiated in the design is automatically set to the POW-
ERDOWN state by the Xilinx ISE development software.
The Power Down pin on the FPGA package has no effect on
, and V
). Voltage regulators can
Module 2 of 4