XC4VFX12-11FFG668I Xilinx Inc, XC4VFX12-11FFG668I Datasheet - Page 41
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XC4VFX12-11FFG668I
Manufacturer Part Number
XC4VFX12-11FFG668I
Description
IC FPGA VIRTEX-4 FX 12K 668FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r
Specifications of XC4VFX12-11FFG668I
Number Of Logic Elements/cells
12312
Number Of Labs/clbs
1368
Total Ram Bits
663552
Number Of I /o
320
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
668-BBGA, FCBGA
For Use With
HW-V4-ML403-UNI-G - EVALUATION PLATFORM VIRTEX-4HW-AFX-FF668-400 - BOARD DEV VIRTEX 4 FF668
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
Regional Clock Buffer - BUFR
R
BUFIO Use Models
In
implementation is ideal in source-synchronous applications where a forwarded clock is
used to capture incoming data.
The regional clock buffer (BUFR) is another new clock buffer available in Virtex-4 devices.
BUFRs drive clock signals to a dedicated clock net within a clock region, independent from
the global clock tree. Each BUFR can drive the two regional clock nets in the region it is
located, and the two clock nets in the adjacent clock regions (up to three clock regions).
Figure
Clock Capable I/O
Clock Capable I/O
1-19, a BUFIO is used to drive the I/O logic using the clock capable I/O. This
Figure 1-19: BUFIO Driving I/O Logic In a Single Clock Region
www.xilinx.com
I/O Tile
I/O Tile
I/O Tile
I/O Tile
I/O Tile
I/O Tile
I/O Tile
I/O Tile
I/O Tile
I/O Tile
I/O Tile
I/O Tile
I/O Tile
I/O Tile
I/O Tile
I/O Tile
BUFIO
Regional Clocking Resources
BUFR
To Adjacent
Region
To Adjacent
Region
ug070_1_19_072204
To Fabric
41
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