XC4VFX12-11FFG668I Xilinx Inc, XC4VFX12-11FFG668I Datasheet - Page 339
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XC4VFX12-11FFG668I
Manufacturer Part Number
XC4VFX12-11FFG668I
Description
IC FPGA VIRTEX-4 FX 12K 668FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r
Specifications of XC4VFX12-11FFG668I
Number Of Logic Elements/cells
12312
Number Of Labs/clbs
1368
Total Ram Bits
663552
Number Of I /o
320
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
668-BBGA, FCBGA
For Use With
HW-V4-ML403-UNI-G - EVALUATION PLATFORM VIRTEX-4HW-AFX-FF668-400 - BOARD DEV VIRTEX 4 FF668
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
R
Verilog Code for Fixed Delay Mode
Variable Delay Mode
The following code shows how to instantiate the IDELAY module in variable delay mode.
IDELAYCTRL must also be instantiated when operating in this mode (see
Overview,” page
VHDL Code for Variable Delay Mode
// The IDELAYCTRL primitive must be instantiated in conjunction with
// IDELAY
// primitive when used in Fixed Delay Mode.
// Module: IDELAY
// Description: Verilog instantiation template
// Fixed Delay Mode
//
// Device: Virtex-4 Family
//-------------------------------------------------------------------
// Instantiation Section
//
IDELAY U1
//Set IOBDELAY_TYPE attribute to FIXED for Fixed Delay Mode
//synthesis attribute IOBDELAY_TYPE of U1 is "FIXED";
//Set IOBDELAY_VALUE attribute to 31 for center of delay element
//synthesis attribute IOBDELAY_VALUE of U1 is 31;
-- The IDELAYCTRL primitive must be instantiated in conjunction with the
IDELAY
-- primitive when used in Variable Delay Mode.
-- Module: IDELAY
-- Description: VHDL instantiation template
-- Variable Delay Mode
--
-- Device: Virtex-4 Family
---------------------------------------------------------------------
-- Components Declarations
-- Component Declaration for IDELAY should be placed
-- after architecture statement but before "begin" keyword
component IDELAY
generic (
(
);
O(data_output)
I(data_input),
C(1’b0),
CE(1’b0),
INC(1’b0),
RST(1’b0)
);
C => ’0’,
CE => ’0’,
INC => ’0’,
RST => ’0’
341).
www.xilinx.com
ILOGIC Resources
“IDELAYCTRL
339
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