XC4VFX12-12SFG363C Xilinx Inc, XC4VFX12-12SFG363C Datasheet - Page 388
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XC4VFX12-12SFG363C
Manufacturer Part Number
XC4VFX12-12SFG363C
Description
IC FPGA VIRTEX-4 FX 12K 363FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r
Specifications of XC4VFX12-12SFG363C
Number Of Logic Elements/cells
12312
Number Of Labs/clbs
1368
Total Ram Bits
663552
Number Of I /o
240
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
363-FBGA, FCBGA
For Use With
HW-V4-ML403-UNI-G - EVALUATION PLATFORM VIRTEX-4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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Part Number:
XC4VFX12-12SFG363C
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Xilinx Inc
Quantity:
10 000
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Chapter 8: Advanced SelectIO Logic Resources
Table 8-7: OSERDES Port List and Definitions
388
OQ
SHIFTOUT1
SHIFTOUT2
TQ
CLK
CLKDIV
D1 – D6
Port Name
OSERDES Primitive
OSERDES Ports
Output
Output
Output
Output
Input
Input
Input
Type
The OSERDES primitive is shown in
Table 8-7
1 (each)
Width
1
1
1
1
1
1
SHIFTIN1
SHIFTIN2
CLK
CLKDIV
D1
D2
D3
D4
D5
D6
OCE
REV
SR
T1
T2
T3
T4
TCE
lists the available ports in the OSERDES primitive.
Data path output.
Carry out for data width expansion. Connect to SHIFTIN1 of master OSERDES.
See
Carry out for data width expansion. Connect to SHIFTIN2 of master OSERDES.
See
3-state control output.
High-speed clock input. Clocks serialized data to OQ output.
Divided clock input. Clocks parallel data at D1-D6 inputs into OSERDES.
Parallel data inputs.
“OSERDES Width
“OSERDES Width
www.xilinx.com
Figure 8-15: OSERDES Primitive
Expansion”.
Expansion”.
Figure
8-15.
Description
UG070 (v2.6) December 1, 2008
Virtex-4 FPGA User Guide
UG070_8_19_031208
SHIFTOUT1
SHIFTOUT2
TQ
OQ
R
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