XC4VFX12-11SFG363I Xilinx Inc, XC4VFX12-11SFG363I Datasheet - Page 55
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XC4VFX12-11SFG363I
Manufacturer Part Number
XC4VFX12-11SFG363I
Description
IC FPGA VIRTEX-4 FX 12K 363FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r
Specifications of XC4VFX12-11SFG363I
Number Of Logic Elements/cells
12312
Number Of Labs/clbs
1368
Total Ram Bits
663552
Number Of I /o
240
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
363-FBGA, FCBGA
For Use With
HW-V4-ML403-UNI-G - EVALUATION PLATFORM VIRTEX-4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Digital Clock Managers (DCMs)
DCM Summary
Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
R
The Virtex®-4 FPGA Digital Clock Managers (DCMs) provide a wide range of powerful
clock management features:
•
•
•
Clock Deskew
The DCM contains a delay-locked loop (DLL) to completely eliminate clock
distribution delays, by deskewing the DCM's output clocks with respect to the input
clock. The DLL contains delay elements (individual small buffers) and control logic.
The incoming clock drives a chain of delay elements, thus the output of every delay
element represents a version of the incoming clock delayed at a different point.
The control logic contains a phase detector and a delay-line selector. The phase
detector compares the incoming clock signal (CLKIN) against a feedback input
(CLKFB) and steers the delay line selector, essentially adding delay to the output of
DCM until the CLKIN and CLKFB coincide.
Frequency Synthesis
Separate outputs provide a doubled frequency (CLK2X and CLK2X180). Another
output, CLKDV, provides a frequency that is a specified fraction of the input
frequency.
Two other outputs, CLKFX and CLKFX180, provide an output frequency derived from
the input clock by simultaneous frequency division and multiplication. The user can
specify any integer multiplier (M) and divisor (D) within the range specified in the
DCM Timing Parameters section of the
determines the appropriate tap selection, to make the output edge coincide with the
input clock whenever mathematically possible. For example, M = 9 and D = 5,
multiply the frequency by 1.8, and the output rising edge is coincident with the input
rising edge after every fifth input period, or after every ninth output period.
Phase Shifting
The DCM allows coarse and fine-grained phase shifting. The coarse phase shifting
uses the 90°, 180°, and 270° phases of CLK0 to make CLK90, CLK180, and CLK270
clock outputs. The 180° phase of CLK2X and CLKFX provide the respective CLK2X180
and CLKFX180 clock outputs.
There are also four modes of fine-grained phase-shifting; fixed, variable-positive,
variable-center, and direct modes. Fine-grained phase shifting allows all DCM output
clocks to be phase-shifted with respect to CLKIN while maintaining the relationship
between the coarse phase outputs. With fixed mode, a fixed fraction of phase shift can
be defined during configuration and in multiples of the clock period divided by 256.
Using the variable-positive and variable-center modes the phase can be dynamically
and repetitively moved forward and backwards by 1/256 of the clock period. With the
www.xilinx.com
Virtex-4 Data
Sheet. An internal calculator
Chapter 2
55
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