XC4VFX12-11SFG363I Xilinx Inc, XC4VFX12-11SFG363I Datasheet - Page 382
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XC4VFX12-11SFG363I
Manufacturer Part Number
XC4VFX12-11SFG363I
Description
IC FPGA VIRTEX-4 FX 12K 363FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r
Specifications of XC4VFX12-11SFG363I
Number Of Logic Elements/cells
12312
Number Of Labs/clbs
1368
Total Ram Bits
663552
Number Of I /o
240
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
363-FBGA, FCBGA
For Use With
HW-V4-ML403-UNI-G - EVALUATION PLATFORM VIRTEX-4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Chapter 8: Advanced SelectIO Logic Resources
382
ISERDES Verilog Instantiation
port map (
// Module: ISERDES
// Description: Verilog instantiation template
//
// Device: Virtex-4 Family
//-------------------------------------------------------------------
// Instantiation Section
//
ISERDES U1
(
.O (data_output),
.Q1 (Q[0]),
.Q2 (Q[1]),
.Q3 (Q[2]),
.Q4 (Q[3]),
.Q5 (open),
.Q6 (open),
.SHIFTOUT1 (open),
.SHIFTOUT2 (open),
.BITSLIP (bitslip),
.CE1 (ce),
);
O => data_output,
Q1 => Q(0),
Q2 => Q(1),
Q3 => Q(2),
Q4 => Q(3),
Q5 => open,
Q6 => open,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
BITSLIP => bitslip,
CE1 => ce,
CE2 => open,
CLK => clk
CLKDIV => clkdiv
D => data_input
DLYCE => dlyce,
DLYINC => dlyinc,
DLYRST => dlyrst,
OCLK => open,
REV => open,
SHIFTIN1 => open,
SHIFTIN2 => open,
SR => rst,
BITSLIP_ENABLE => "FALSE", --(TRUE, FALSE)
DATA_RATE => "DDR", --(SDR, DDR)
DATA_WIDTH => 4, --(2,3,4,5,6,7,8,10)
INTERFACE_TYPE => "MEMORY", --(MEMORY, NETWORKING)
IOBDELAY => "NONE", --(NONE,IBUF,IFD,BOTH)
IOBDELAY_TYPE => "DEFAULT", --(DEFAULT, FIXED, VARIABLE)
IOBDELAY_VALUE => 0, --(0 to 63)
NUM_CE => 2, --(1,2)
SERDES_MODE => "MASTER", --(MASTER, SLAVE)
);
www.xilinx.com
UG070 (v2.6) December 1, 2008
Virtex-4 FPGA User Guide
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