XC4VFX12-10SFG363I Xilinx Inc, XC4VFX12-10SFG363I Datasheet - Page 362
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XC4VFX12-10SFG363I
Manufacturer Part Number
XC4VFX12-10SFG363I
Description
IC FPGA VIRTEX-4 FX 12K 363FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r
Specifications of XC4VFX12-10SFG363I
Number Of Logic Elements/cells
12312
Number Of Labs/clbs
1368
Total Ram Bits
663552
Number Of I /o
240
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
363-FBGA, FCBGA
For Use With
HW-V4-ML403-UNI-G - EVALUATION PLATFORM VIRTEX-4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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Price
Company:
Part Number:
XC4VFX12-10SFG363I
Manufacturer:
Xilinx Inc
Quantity:
10 000
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Chapter 7: SelectIO Logic Resources
362
Figure 7-28
Clock Event 1
•
•
Clock Event 2
•
Figure 7-29
in opposite edge mode. For other modes add the appropriate latencies as shown in
Figure 7-7, page
CE
SR
TQ
T1
C
At time T
High at the TCE input of the 3-state register, enabling the 3-state register for incoming
data.
At time T
input of the 3-state register, returning the pad to high-impedance at time T
Clock Event 1.
At time T
in this case) becomes valid-High, resetting the 3-state register at time T
Event 2.
T
OCKQ
illustrates the OLOGIC 3-state register timing.
Figure 7-28: OLOGIC 3-State Register Timing Characteristics
illustrates IOB DDR 3-state register timing. This example is shown using DDR
OTCECK
OTCK
OSRCK
326.
1
before Clock Event 1 the 3-state signal becomes valid-High at the T
before Clock Event 2, the SR signal (configured as synchronous reset
before Clock Event 1, the 3-state clock enable signal becomes valid-
T
T
OTCK
OTCECK
www.xilinx.com
2
T
OSRCK
T
RQ
3
UG070 (v2.6) December 1, 2008
4
Virtex-4 FPGA User Guide
RQ
UG070_7_28_080204
5
after Clock
OCKQ
after
R
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