XC4VFX12-10SFG363C Xilinx Inc, XC4VFX12-10SFG363C Datasheet - Page 393
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XC4VFX12-10SFG363C
Manufacturer Part Number
XC4VFX12-10SFG363C
Description
IC FPGA VIRTEX-4 FX 12K 363FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r
Datasheets
1.XC4VFX12-10FFG668C.pdf
(58 pages)
2.XC4VFX12-10FFG668C.pdf
(9 pages)
3.XC4VFX12-10FFG668C.pdf
(406 pages)
Specifications of XC4VFX12-10SFG363C
Number Of Logic Elements/cells
12312
Number Of Labs/clbs
1368
Total Ram Bits
663552
Number Of I /o
240
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
363-FBGA, FCBGA
Package
363FCBGA
Family Name
Virtex®-4
Device Logic Units
12312
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
240
Ram Bits
663552
For Use With
HW-V4-ML403-UNI-G - EVALUATION PLATFORM VIRTEX-4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC4VFX12-10SFG363C
Manufacturer:
Xilinx Inc
Quantity:
10 000
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Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
R
Guidelines for Expanding the Parallel-to-Serial Converter Bit Width
Figure 8-17
master and slave OSERDES modules. Ports D3–D6 are used for the last four bits of the
parallel interface on the slave OSERDES (LSB to MSB).
Table 8-9
Table 8-9: OSERDES SDR/DDR Data Width Availability
1.
2.
3.
4.
5.
Table 8-10
Table 8-10: Slave Inputs Used for Data Width Expansion
SDR Data Widths
DDR Data Widths
Data Inputs[0:5]
Data Inputs[6:9]
Both the OSERDES modules must be adjacent master and slave pairs.
Set the SERDES_MODE attribute for the master OSERDES to MASTER and the slave
OSERDES to SLAVE (see
The user must connect the SHIFTIN ports of the MASTER to the SHIFTOUT ports of
the SLAVE.
The SLAVE only uses the ports D3 to D6 as an input.
Master and Slave have the same DATA_WIDTH attribute value.
lists the data width availability for SDR and DDR mode.
Data Width
shows the slave inputs used for data widths requiring width expansion.
illustrates a block diagram of a 10:1 DDR parallel-to-serial converter using the
Figure 8-17: Block Diagram of OSERDES Width Expansion
10
7
8
www.xilinx.com
“SERDES_MODE
Output Parallel-to-Serial Logic Resources (OSERDES)
2, 3, 4, 5, 6, 7, 8
4, 6, 8, 10
SERDES_MODE = MASTER
D1
D2
D3
D4
D5
D6
D1
D2
D3
D4
D5
D6
SERDES_MODE=SLAVE
Slave Inputs Used
SHIFTOUT1 SHIFTOUT2
SHIFTIN1
OSERDES
OSERDES
D3–D4
D3–D6
(Master)
(Slave)
D3
Attribute”).
SHIFTIN2
OQ
OQ
ug070_8_20_073004
Data Out
393
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