XC4VFX12-10SFG363C Xilinx Inc, XC4VFX12-10SFG363C Datasheet - Page 327
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XC4VFX12-10SFG363C
Manufacturer Part Number
XC4VFX12-10SFG363C
Description
IC FPGA VIRTEX-4 FX 12K 363FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r
Datasheets
1.XC4VFX12-10FFG668C.pdf
(58 pages)
2.XC4VFX12-10FFG668C.pdf
(9 pages)
3.XC4VFX12-10FFG668C.pdf
(406 pages)
Specifications of XC4VFX12-10SFG363C
Number Of Logic Elements/cells
12312
Number Of Labs/clbs
1368
Total Ram Bits
663552
Number Of I /o
240
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
363-FBGA, FCBGA
Package
363FCBGA
Family Name
Virtex®-4
Device Logic Units
12312
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
240
Ram Bits
663552
For Use With
HW-V4-ML403-UNI-G - EVALUATION PLATFORM VIRTEX-4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC4VFX12-10SFG363C
Manufacturer:
Xilinx Inc
Quantity:
10 000
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Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
Input DDR Primitive (IDDR)
R
Figure 7-8
signals.
primitive.
Table 7-3: IDDR Port Signals
Table 7-4: IDDR Attributes
Q1 and Q2
C
CE
D
R
S
DDR_CLK_EDGE
INIT_Q1
INIT_Q2
SRTYPE
Attribute Name
Name
Port
Table 7-4
shows the block diagram of the IDDR primitive.
Data outputs
Clock input port
Clock enable port
Data input (DDR)
Reset
Set
describes the various attributes available and default values for the IDDR
Function
Sets the IDDR mode of operation
with respect to clock edge
Sets the initial value for Q1 port
Sets the initial value for Q2 port
Set/Reset type with respect to
clock (C)
Figure 7-8: IDDR Primitive Block Diagram
www.xilinx.com
CE
D
C
Description
IDDR register outputs. Q1 is rising edge data, Q2 is
falling edge data.
The C pin represents the clock input pin.
The enable pin affects the loading of data into the DDR
flip-flop. When Low, clock transitions are ignored and
new data is not loaded into the DDR flip-flop. CE must
be High to load new data into the DDR flip-flop.
IDDR register input from IOB.
Synchronous/Asynchronous reset pin. Reset is asserted
High.
Synchronous/Asynchronous set pin. Set is asserted
High.
R
S
IDDR
ug070_7_08_071404
Q1
Q2
Description
OPPOSITE_EDGE (default),
SAME_EDGE,
SAME_EDGE_PIPELINED
0 (default), 1
0 (default), 1
ASYNC, SYNC (default)
Table 7-3
Possible Values
lists the IDDR port
ILOGIC Resources
327
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