XC4VFX12-10SFG363C Xilinx Inc, XC4VFX12-10SFG363C Datasheet - Page 242
![no-image](/images/no-image-200.jpg)
XC4VFX12-10SFG363C
Manufacturer Part Number
XC4VFX12-10SFG363C
Description
IC FPGA VIRTEX-4 FX 12K 363FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r
Datasheets
1.XC4VFX12-10FFG668C.pdf
(58 pages)
2.XC4VFX12-10FFG668C.pdf
(9 pages)
3.XC4VFX12-10FFG668C.pdf
(406 pages)
Specifications of XC4VFX12-10SFG363C
Number Of Logic Elements/cells
12312
Number Of Labs/clbs
1368
Total Ram Bits
663552
Number Of I /o
240
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
363-FBGA, FCBGA
Package
363FCBGA
Family Name
Virtex®-4
Device Logic Units
12312
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
240
Ram Bits
663552
For Use With
HW-V4-ML403-UNI-G - EVALUATION PLATFORM VIRTEX-4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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Company:
Part Number:
XC4VFX12-10SFG363C
Manufacturer:
Xilinx Inc
Quantity:
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Chapter 6: SelectIO Resources
242
1.
2.
3.
4.
5.
6.
7.
8.
V
IOSTANDARDs in that bank.
Correct DCI I/O buffers must be used in the software either by using IOSTANDARD
attributes or instantiations in the HDL code.
Some DCI standards require that external reference resistors be connected to
multipurpose pins VRP and VRN in the bank. Where this is required, these two
multipurpose pins cannot be used as regular user I/Os. Refer to the Virtex-4 FPGA
pinouts for the specific pin locations. Pin VRN must be pulled up to V
reference resistor. Pin VRP must be pulled down to ground by its reference resistor.
However, some DCI standards do not require external reference resistors on the
VRP/VRN pins. If these are the only DCI-based I/O standards in a bank, the VRP and
VRN pins in that bank can be used as general-purpose I/Os.
♦
♦
The value of the external reference resistors should be selected to give the desired
output impedance. If using GTL_DCI, HSTL_DCI, or SSTL_DCI I/O standards, then
the external reference resistors should be 50Ω.
The values of the reference resistors must be within the supported range (20Ω – 100Ω).
Follow the DCI I/O banking rules:
a.
b. V
c.
d. No more than one DCI I/O standard using split termination type is allowed per
e.
The following packages to not support DCI in Banks 1 and 2: SF363, FF668, FF676,
FF672, and FF1152.
In addition, the following devices do not support DCI in Banks 1 and 2: XC4VLX15,
XC4VLX25, XC4VSX25, XC4VSX35, XC4VFX12, XC4VFX20, XC4VFX40, and
XC4VFX60.
CCO
The following DCI outputs do not require reference resistors on VRP/VRN:
HSTL_I_DCI
HSTL_III_DCI
HSTL_I_DCI_18
HSTL_III_DCI_18
SSTL2_I_DCI
SSTL18_I_DCI
The following inputs do not require reference resistors on VRP/VRN:
LVDCI_15
LVDCI_18
LVDCI_25
LVDCI_33
LVDCI_DV2_15
LVDCI_DV2_18
LVDCI_DV2_25
LVDCI_DV2_33
V
No more than one DCI I/O standard using single termination type is allowed per
bank.
bank.
Single termination and split termination, controlled impedance driver, and
controlled impedance driver with half impedance can co-exist in the same bank.
REF
CCO
pins must be connected to the appropriate V
must be compatible for all of the inputs in the same bank.
must be compatible for all of the inputs and outputs in the same bank.
www.xilinx.com
CCO
voltage based on the
UG070 (v2.6) December 1, 2008
Virtex-4 FPGA User Guide
CCO
by its
R
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