XC4VFX12-10SFG363C Xilinx Inc, XC4VFX12-10SFG363C Datasheet - Page 123
![no-image](/images/no-image-200.jpg)
XC4VFX12-10SFG363C
Manufacturer Part Number
XC4VFX12-10SFG363C
Description
IC FPGA VIRTEX-4 FX 12K 363FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r
Datasheets
1.XC4VFX12-10FFG668C.pdf
(58 pages)
2.XC4VFX12-10FFG668C.pdf
(9 pages)
3.XC4VFX12-10FFG668C.pdf
(406 pages)
Specifications of XC4VFX12-10SFG363C
Number Of Logic Elements/cells
12312
Number Of Labs/clbs
1368
Total Ram Bits
663552
Number Of I /o
240
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
363-FBGA, FCBGA
Package
363FCBGA
Family Name
Virtex®-4
Device Logic Units
12312
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
240
Ram Bits
663552
For Use With
HW-V4-ML403-UNI-G - EVALUATION PLATFORM VIRTEX-4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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Quantity
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Company:
Part Number:
XC4VFX12-10SFG363C
Manufacturer:
Xilinx Inc
Quantity:
10 000
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Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
Byte-Wide Write Enable
R
The byte-wide write enable feature of the block RAM gives the capability to write eight bit
(one byte) portions of incoming data. There are four independent byte-write enable inputs.
Each byte-write enable is associated with one byte of input data and one parity bit. All four
byte-write enable inputs must be driven in all data width configurations. This feature is
useful when using block RAM to interface with the PPC405. Byte-write enable is not
available in the Multi-rate FIFO. Byte-write enable is further described in the
RAMB16 Primitive Design Considerations”
enable logic.
When configured for a 36-bit or 18-bit wide data path, any port can restrict writing to
specified byte locations within the data word. If configured in READ_FIRST mode, the DO
bus shows the previous content of the whole addressed word. In WRITE_FIRST mode,
with identical Read and Write port widths, DO shows only the enabled newly written
byte(s). The other byte values must be ignored. In WRITE_FIRST mode with different
widths for Read and Write ports, all data on DO must be ignored.
WE[3:0]
A[13:0]
A14
DI
RAM_EXTENSION =
4
Figure 4-8: Byte-Wide Write Enable In Block RAM
NONE(0)
0
1
www.xilinx.com
Additional Block RAM Features in Virtex-4 Devices
“00”
D
D
D
D
D
section.
4
Figure 4-8
A[13:0]
A14
WE_Control
DI
WE[3:0]
shows the byte-wide write-
DO
UG070_4_08_033005
“Additional
DO
123
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