XC4VFX12-10SFG363C Xilinx Inc, XC4VFX12-10SFG363C Datasheet - Page 117
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XC4VFX12-10SFG363C
Manufacturer Part Number
XC4VFX12-10SFG363C
Description
IC FPGA VIRTEX-4 FX 12K 363FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r
Datasheets
1.XC4VFX12-10FFG668C.pdf
(58 pages)
2.XC4VFX12-10FFG668C.pdf
(9 pages)
3.XC4VFX12-10FFG668C.pdf
(406 pages)
Specifications of XC4VFX12-10SFG363C
Number Of Logic Elements/cells
12312
Number Of Labs/clbs
1368
Total Ram Bits
663552
Number Of I /o
240
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
363-FBGA, FCBGA
Package
363FCBGA
Family Name
Virtex®-4
Device Logic Units
12312
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
240
Ram Bits
663552
For Use With
HW-V4-ML403-UNI-G - EVALUATION PLATFORM VIRTEX-4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC4VFX12-10SFG363C
Manufacturer:
Xilinx Inc
Quantity:
10 000
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Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
R
Table 4-1: Dual-Port Names and Descriptions
Notes:
1. The
SSR[A|B]
CLK[A|B]
DO[A|B]
DOP[A|B]
DI[A|B]
DIP[A|B]
ADDR[A|B]
WE[A|B]
EN[A|B]
REGCE[A|B]
CASCADEIN[A|B]
CASCADEOUT[A|B]
“Data Parity Buses - DIP[A/B] and DOP[A/B]”
Port Name
(1)
(1)
www.xilinx.com
Figure 4-1: Dual-Port Data Flows
CASCADEOUTA
CASCADEINA
Data Input Bus
Data Input Parity Bus
Address Bus
Write Enable
When inactive no data is written to the block RAM and the
output bus remains in its previous state.
Set/Reset
Clock Input
Data Output Bus
Data Output Parity Bus
Output Register Enable
Cascade input pin for 32K x 1 mode
Cascade output pin for 32K x 1 mode
DIA
DIPA
ADDRA
WEA
ENA
SSRA
REGCEA
DIB
DIPB
ADDRB
WEB
ENB
SSRB
REGCEB
CLKA
CLKB
18-Kbit Block RAM
Synchronous Dual-Port and Single-Port RAMs
Memory
Port A
Port B
18 Kb
Array
CASCADEOUTB
section has more information on Data Parity pins.
CASCADEINB
DOPA
DOPB
DOA
DOB
Description
ug070_4_01_071204
117
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