XC3SD1800A-4FGG676I Xilinx Inc, XC3SD1800A-4FGG676I Datasheet - Page 27
![SPARTAN-3ADSP FPGA 1800K 676FBGA](/photos/6/73/67300/b-676_sml.jpg)
XC3SD1800A-4FGG676I
Manufacturer Part Number
XC3SD1800A-4FGG676I
Description
SPARTAN-3ADSP FPGA 1800K 676FBGA
Manufacturer
Xilinx Inc
Series
Spartan™-3A DSPr
Datasheets
1.XC3S50A-4VQG100C.pdf
(7 pages)
2.XC3SD3400A-4FGG676C.pdf
(4 pages)
3.XC3SD3400A-4FGG676C.pdf
(101 pages)
Specifications of XC3SD1800A-4FGG676I
Total Ram Bits
1548288
Number Of Logic Elements/cells
37440
Number Of Labs/clbs
4160
Number Of I /o
519
Number Of Gates
1800000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
676-BBGA
No. Of Logic Blocks
4224
No. Of Gates
1800000
No. Of Macrocells
37440
Family Type
Spartan-3A
No. Of Speed Grades
4
No. Of I/o's
519
Clock
RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
122-1574 - KIT DEVELOPMENT SPARTAN 3ADSP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3SD1800A-4FGG676I
Manufacturer:
XILINX
Quantity:
591
Company:
Part Number:
XC3SD1800A-4FGG676I
Manufacturer:
Xilinx Inc
Quantity:
10 000
Company:
Part Number:
XC3SD1800A-4FGG676I
Manufacturer:
XILINX
Quantity:
160
Output Propagation Times
Table 23: Timing for the IOB Output Path
DS610 (v3.0) October 4, 2010
Product Specification
Notes:
1.
2.
Clock-to-Output Times
Propagation Times
Set/Reset Times
T
Symbol
The numbers in this table are tested using the methodology presented in
Table 7
This time requires adjustment whenever a signal standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data
Output. When this is true, add the appropriate Output adjustment from
T
T
T
IOGSRQ
IOCKP
IOSRP
IOOP
and
Table
When reading from the Output
Flip-Flop (OFF), the time from the
active transition at the OCLK input to
data appearing at the Output pin
The time it takes for data to travel from
the IOB’s O input to the Output pin
Time from asserting the OFF’s SR
input to setting/resetting data at the
Output pin
Time from asserting the Global Set
Reset (GSR) input on the
STARTUP_SPARTAN3A primitive to
setting/resetting data at the Output pin
10.
Description
LVCMOS25
drive, Fast slew rate
LVCMOS25
drive, Fast slew rate
LVCMOS25
drive, Fast slew rate
Spartan-3A DSP FPGA Family: DC and Switching Characteristics
www.xilinx.com
Conditions
(2)
(2)
(2)
Table
, 12 mA output
, 12 mA output
, 12 mA output
Table 26
25.
and are based on the operating conditions set forth in
Device
All
All
All
Max
2.87
2.78
3.63
8.62
Speed Grade
-5
Max
3.13
2.91
3.89
9.65
-4
Units
ns
ns
ns
ns
27