XC3SD1800A-5CS484C Xilinx Inc, XC3SD1800A-5CS484C Datasheet - Page 84
![SPARTAN-3ADSP FPGA 1800K 484CSA](/photos/6/73/67348/pk223-cs484_sml.jpg)
XC3SD1800A-5CS484C
Manufacturer Part Number
XC3SD1800A-5CS484C
Description
SPARTAN-3ADSP FPGA 1800K 484CSA
Manufacturer
Xilinx Inc
Series
Spartan™-3A DSPr
Datasheets
1.XC3S50A-4VQG100C.pdf
(7 pages)
2.XC3SD3400A-4FGG676C.pdf
(4 pages)
3.XC3SD3400A-4FGG676C.pdf
(101 pages)
Specifications of XC3SD1800A-5CS484C
Number Of Logic Elements/cells
37440
Number Of Labs/clbs
4160
Total Ram Bits
1548288
Number Of I /o
309
Number Of Gates
1800000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA, CSPBGA
For Use With
122-1574 - KIT DEVELOPMENT SPARTAN 3ADSP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3SD1800A-5CS484C
Manufacturer:
XILINX
Quantity:
648
Part Number:
XC3SD1800A-5CS484C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
User I/Os by Bank
Table 67
AWAKE pin is counted as a dual-purpose I/O.
Table 67: User I/Os Per Bank for the XC3SD1800A in the FG676 Package
DS610 (v3.0) October 4, 2010
Product Specification
Notes:
1.
Top
Right
Bottom
Left
Package
TOTAL
28 VREF are on INPUT pins.
Edge
indicates how the available user-I/O pins are distributed between the four I/O banks on the FG676 package. The
I/O Bank
0
1
2
3
Maximum I/Os
Input-Only
and
128
130
129
132
519
314
I/O
82
67
68
97
www.xilinx.com
INPUT
Spartan-3A DSP FPGA Family: Pinout Descriptions
28
15
21
18
82
All Possible I/O Pins by Type
DUAL
30
21
52
1
0
VREF
10
11
39
9
9
(1)
CLK
32
8
8
8
8
84