XC3SD1800A-5CS484C Xilinx Inc, XC3SD1800A-5CS484C Datasheet - Page 46
![SPARTAN-3ADSP FPGA 1800K 484CSA](/photos/6/73/67348/pk223-cs484_sml.jpg)
XC3SD1800A-5CS484C
Manufacturer Part Number
XC3SD1800A-5CS484C
Description
SPARTAN-3ADSP FPGA 1800K 484CSA
Manufacturer
Xilinx Inc
Series
Spartan™-3A DSPr
Datasheets
1.XC3S50A-4VQG100C.pdf
(7 pages)
2.XC3SD3400A-4FGG676C.pdf
(4 pages)
3.XC3SD3400A-4FGG676C.pdf
(101 pages)
Specifications of XC3SD1800A-5CS484C
Number Of Logic Elements/cells
37440
Number Of Labs/clbs
4160
Total Ram Bits
1548288
Number Of I /o
309
Number Of Gates
1800000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA, CSPBGA
For Use With
122-1574 - KIT DEVELOPMENT SPARTAN 3ADSP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3SD1800A-5CS484C
Manufacturer:
XILINX
Quantity:
648
Part Number:
XC3SD1800A-5CS484C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
Table 37: Switching Characteristics for the DLL (Cont’d)
Digital Frequency Synthesizer (DFS)
Table 38: Recommended Operating Conditions for the DFS
DS610 (v3.0) October 4, 2010
Product Specification
Notes:
1.
2.
3.
4.
5.
Notes:
1.
2.
3.
4.
5.
Delay Lines
DCM_DELAY_STEP
Input Frequency Ranges
F
Input Clock Jitter Tolerance
CLKIN_CYC_JITT_FX_LF
CLKIN_CYC_JITT_FX_HF
CLKIN_PER_JITT_FX
CLKIN
The numbers in this table are based on the operating conditions set forth in
Indicates the maximum amount of output jitter that the DCM adds to the jitter on the CLKIN input.
For optimal jitter tolerance and faster lock time, use the CLKIN_PERIOD attribute.
Some jitter and duty-cycle specifications include 1% of input clock period or 0.01 UI. For example, the data sheet specifies a maximum jitter
of ±[1% of CLKIN period + 150]. Assume the CLKIN frequency is 100 MHz. The equivalent CLKIN period is 10 ns and 1% of 10 ns is 0.1 ns
or 100 ps. According to the data sheet, the maximum jitter is ±[100 ps + 150 ps] = ±250 ps, averaged over all steps.
The typical delay step size is 23 ps.
DFS specifications apply when either of the DFS outputs (CLKFX or CLKFX180) are used.
If both DFS and DLL outputs are used on the same DCM, follow the more restrictive CLKIN_FREQ_DLL specifications in
CLKIN input jitter beyond these limits may cause the DCM to lose lock.
The DCM specifications are guaranteed when both adjacent DCMs are locked.
To support double the maximum effective F
clock frequency by two as it enters the DCM.
Symbol
CLKIN_FREQ_FX
Symbol
(5)
(2)
Finest delay resolution, averaged over all steps
(3)
Frequency for the CLKIN input
Cycle-to-cycle jitter at the
CLKIN input, based on CLKFX
output frequency
Period jitter at the CLKIN input
CLKIN
Description
limit, set the CLKIN_DIVIDE_BY_2 attribute to TRUE. This attribute divides the incoming
Description
Spartan-3A DSP FPGA Family: DC and Switching Characteristics
www.xilinx.com
F
F
CLKFX
CLKFX
< 150 MHz
> 150 MHz
Table 7
and
Device
Table
All
Min
0.2
–
–
–
36.
Min
15
-5
333
±300
±150
Speed Grade
Max
±1
-5
(5)
Speed Grade
Max
35
Min
0.2
–
–
–
Min
15
-4
-4
Table
333
±300
±150
Max
±1
Max
35
(5)
36.
Units
MHz
Units
ps
ps
ns
ps
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