EP2SGX90EF1152C3ES Altera, EP2SGX90EF1152C3ES Datasheet - Page 32
EP2SGX90EF1152C3ES
Manufacturer Part Number
EP2SGX90EF1152C3ES
Description
IC STRATIX II GX 90K 1152-FBGA
Manufacturer
Altera
Series
Stratix® II GXr
Datasheet
1.EP2SGX30DF780C5.pdf
(316 pages)
Specifications of EP2SGX90EF1152C3ES
Number Of Logic Elements/cells
90960
Number Of Labs/clbs
4548
Total Ram Bits
4520448
Number Of I /o
558
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 70°C
Package / Case
1152-FBGA
For Use With
544-1725 - PCIE KIT W/S II GX EP2SGX90N544-1724 - SI KIT W/SII GX EP2SGX90N544-1702 - VIDEO KIT W/SII GX EP2SGX90N
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Other names
544-1763
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Transceivers
Figure 2–19. Before and After the Channel Aligner
2–24
Stratix II GX Device Handbook, Volume 1
Lane 3
Lane 3
Lane 2
Lane 1
Lane 0
Lane 1
The rx_syncstatus signal is not available in bit-slipping mode.
Channel Aligner
The channel aligner is available only in XAUI mode and aligns the signals
of all four channels within a transceiver. The channel aligner follows the
IEEE 802.3ae, clause 48 specification for channel bonding.
The channel aligner is a 16-word FIFO buffer with a state machine
controlling the channel bonding process. The state machine looks for an
/A/ (/K28.3/) in each channel, and aligns all the /A/ code groups in the
transceiver. When four columns of /A/ (denoted by //A//) are
detected, the rx_channelaligned signal goes high, signifying that all
the channels in the transceiver have been aligned. The reception of four
consecutive misaligned /A/ code groups restarts the channel alignment
sequence and sends the rx_channelaligned signal low.
Figure 2–19
the aligned channels after the channel aligner.
Lane 0
Lane 2
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shows misaligned channels before the channel aligner and
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Altera Corporation
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October 2007
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