EP2SGX90EF1152C3ES Altera, EP2SGX90EF1152C3ES Datasheet - Page 102
EP2SGX90EF1152C3ES
Manufacturer Part Number
EP2SGX90EF1152C3ES
Description
IC STRATIX II GX 90K 1152-FBGA
Manufacturer
Altera
Series
Stratix® II GXr
Datasheet
1.EP2SGX30DF780C5.pdf
(316 pages)
Specifications of EP2SGX90EF1152C3ES
Number Of Logic Elements/cells
90960
Number Of Labs/clbs
4548
Total Ram Bits
4520448
Number Of I /o
558
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 70°C
Package / Case
1152-FBGA
For Use With
544-1725 - PCIE KIT W/S II GX EP2SGX90N544-1724 - SI KIT W/SII GX EP2SGX90N544-1702 - VIDEO KIT W/SII GX EP2SGX90N
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Other names
544-1763
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PLLs and Clock Networks
Figure 2–66. EP2SGX60, EP2SGX90 and EP2SGX130 Device I/O Clock Groups
2–94
Stratix II GX Device Handbook, Volume 1
IO_CLKM[7..0]
IO_CLKO[7..0]
IO_CLKN[7..0]
IO_CLKP[7..0]
8
8
8
8
IO_CLKA[7..0]
8
IO_CLKL[7..0]
You can use the Quartus II software to control whether a clock input pin
drives either a global, regional, or dual-regional clock network. The
Quartus II software automatically selects the clocking resources if not
specified.
Clock Control Block
Each global clock, regional clock, and PLL external clock output has its
own clock control block. The control block has two functions:
■
■
24 Clocks in the
24 Clocks in the
8
Quadrant
Quadrant
Clock source selection (dynamic selection for global clocks)
Clock power-down (dynamic clock enable or disable)
IO_CLKB[7..0]
8
IO_CLKK[7..0]
8
IO_CLKC[7..0]
8
IO_CLKJ[7..0]
24 Clocks in the
24 Clocks in the
8
Quadrant
Quadrant
IO_CLKD[7..0]
8
IO_CLKI[7..0]
8
Altera Corporation
8
8
8
8
October 2007
IO_CLKE[7..0]
IO_CLKF[7..0]
IO_CLKG[7..0]
IO_CLKH[7..0]
I/O Clock Regions
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