EP2S130F780C5N Altera, EP2S130F780C5N Datasheet - Page 45
EP2S130F780C5N
Manufacturer Part Number
EP2S130F780C5N
Description
IC STRATIX II FPGA 130K 780-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S130F780C5N
Number Of Logic Elements/cells
132540
Number Of Labs/clbs
6627
Total Ram Bits
6747840
Number Of I /o
534
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Family Name
Stratix II
Number Of Logic Blocks/elements
132540
# I/os (max)
534
Frequency (max)
609.76MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
132540
Ram Bits
6747840
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S130F780C5N
Manufacturer:
ALTERA
Quantity:
591
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Figure 2–25. M-RAM Block LAB Row Interface
Note to
(1)
Altera Corporation
May 2007
Only R24 and C16 interconnects cross the M-RAM block boundaries.
Figure
LABs in Row
M-RAM Boundary
2–25:
Row Unit Interface Allows LAB
Rows to Drive Port A Datain,
Dataout, Address and Control
Signals to and from M-RAM Block
LAB Interface
Blocks
L0
L1
L2
L3
L4
L5
Port A
Note (1)
M-RAM Block
Row Unit Interface Allows LAB
Rows to Drive Port B Datain,
Dataout, Address and Control
Signals to and from M-RAM Block
Stratix II Device Handbook, Volume 1
Port B
R0
R1
R2
R3
R4
R5
LABs in Row
M-RAM Boundary
Stratix II Architecture
2–37
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