EP2S130F780C5N Altera, EP2S130F780C5N Datasheet - Page 42
EP2S130F780C5N
Manufacturer Part Number
EP2S130F780C5N
Description
IC STRATIX II FPGA 130K 780-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S130F780C5N
Number Of Logic Elements/cells
132540
Number Of Labs/clbs
6627
Total Ram Bits
6747840
Number Of I /o
534
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Family Name
Stratix II
Number Of Logic Blocks/elements
132540
# I/os (max)
534
Frequency (max)
609.76MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
132540
Ram Bits
6747840
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S130F780C5N
Manufacturer:
ALTERA
Quantity:
591
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TriMatrix Memory
Figure 2–22. M4K RAM Block LAB Row Interface
2–34
Stratix II Device Handbook, Volume 1
Direct link
interconnect
to adjacent LAB
Direct link
interconnect
from adjacent LAB
C4 Interconnect
M4K RAM Block Local
Interconnect Region
16
M-RAM Block
The largest TriMatrix memory block, the M-RAM block, is useful for
applications where a large volume of data must be stored on-chip. Each
block contains 589,824 RAM bits (including parity bits). The M-RAM
block can be configured in the following modes:
■
■
■
■
You cannot use an initialization file to initialize the contents of an M-RAM
block. All M-RAM block contents power up to an undefined value. Only
synchronous operation is supported in the M-RAM block, so all inputs
are registered. Output registers can be bypassed.
True dual-port RAM
Simple dual-port RAM
Single-port RAM
FIFO
datain
control
signals
clocks
LAB Row Clocks
M4K RAM
address
Block
dataout
byte
enable
36
6
Altera Corporation
Direct link
interconnect
to adjacent LAB
Direct link
interconnect
from adjacent LAB
R4 Interconnect
May 2007
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