EP3SL150F780C2N Altera, EP3SL150F780C2N Datasheet - Page 37

• Manufacturer Part Number: EP3SL150F780C2N
• Description: IC STRATIX III FPGA 150K 780FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F780C2N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 488
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Stratix III
• Number Of Logic Blocks/elements: 142500
• # I/os (max): 488
• Frequency (max): 600MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.1V
• Logic Cells: 142500
• Ram Bits: 6543360
• Operating Supply Voltage (min): 1.05V
• Operating Supply Voltage (max): 1.15V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2405; EP3SL150F780C2NES

Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
Programmable IOE Delay
Table 1–39. IOE Programmable Delay for Stratix III Devices
© July 2010 Altera Corporation
Parameter
Notes to
(1) You can set the parameter values in the Quartus II software by selecting D1, D2, D3, D4, D5, and D6 in the Assignment Name column.
(2) The minimum offset represented in this table does not include the intrinsic delay.
D1
D2
D3
D4
D5
D6
Table
Available
Settings
1–39:
15
15
15
7
7
6
Table 1–38. Default Loading of Various I/O Standards for Stratix III Devices (Part 2 of 2)
Table 1–39
Differential SSTL-18 CLASS II
1.8-V Differential HSTL CLASS I
1.8-V Differential HSTL CLASS II
1.5-V Differential HSTL CLASS I
1.5-V Differential HSTL CLASS II
1.2-V Differential HSTL CLASS I
1.2-V Differential HSTL CLASS II
LVDS
Offset
Min
f
(2)
0
0
0
0
0
0
Offset
1625
Max
442
248
491
452
179
lists the Stratix III IOE programmable delay settings.
Fast Model
For more information about the annotation of delays in the IOE, refer to
Figure 7–7 in the
Offset
1806
Max
491
285
517
503
199
Offset
2747
I/O Standard
Max
748
387
726
764
305
C2
Stratix III Device I/O Features
Offset
(Note 1)
3058
Max
829
412
872
801
337
C3
Offset
3371
Max
916
442
884
930
370
C4
Offset
3218
Max
871
427
844
887
354
C4L
Offset
3084
Max
833
411
808
850
339
chapter.
Stratix III Device Handbook, Volume 2
Offset
3210
Max
870
433
845
889
354
I3
Capacitive
Load
0
0
0
0
0
0
0
0
Offset
3540
Max
957
464
928
977
389
I4
Offset
3382
Max
915
448
887
932
371
Unit
pF
pF
pF
pF
pF
pF
pF
pF
I4L
Offset
1–37
3084
Max
833
411
808
850
339
Unit
ps
ps
ps
ps
ps
ps