EP3SL150F780C2N Altera, EP3SL150F780C2N Datasheet - Page 321

• Manufacturer Part Number: EP3SL150F780C2N
• Description: IC STRATIX III FPGA 150K 780FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F780C2N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 488
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Stratix III
• Number Of Logic Blocks/elements: 142500
• # I/os (max): 488
• Frequency (max): 600MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.1V
• Logic Cells: 142500
• Ram Bits: 6543360
• Operating Supply Voltage (min): 1.05V
• Operating Supply Voltage (max): 1.15V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2405; EP3SL150F780C2NES

Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
Table 1–184. EP3SE80 Column Pin Global Clock Timing Specifications
Table 1–185. EP3SE80 Row Pin Global Clock Timing Specifications
Table 1–186. EP3SE80 Column Pin Regional Clock Timing Specifications
Table 1–187. EP3SE80 Row Pin Regional Clock Timing Specifications
© July 2010 Altera Corporation
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Parameter
Parameter
Parameter
Parameter
CIN
COUT
PLLCIN
PLLCOUT
CIN
COUT
PLLCIN
PLLCOUT
CIN
COUT
PLLCIN
PLLCOUT
CIN
COUT
PLLCIN
PLLCOUT
Industrial
Industrial
Industrial
Industrial
-0.024
-0.024
-0.062
-0.013
-0.013
-0.072
2.037
2.037
1.994
1.912
0.020
1.828
1.828
1.812
1.730
0.010
Fast Model
Fast Model
Fast Model
Fast Model
EP3SE80 Clock Timing Parameters
Table 1–184
devices.
Table 1–186
devices.
Commercial
Commercial
Commercial
Commercial
-0.007
-0.007
-0.005
-0.004
2.059
2.059
2.143
2.052
0.086
1.849
1.849
0.004
0.004
1.928
1.837
0.087
and
and
Table 1–185
Table 1–187
-0.235 -0.315 -0.292
-0.235 -0.315 -0.292
-0.177 -0.249 -0.221
-0.319 -0.412 -0.402
-0.224 -0.303 -0.280
-0.224 -0.303 -0.280
-0.176 -0.259 -0.231
-0.318 -0.422 -0.412
2.879
2.879
2.942
2.800
2.578
2.578
2.638
2.496
1.1 V
1.1 V
1.1 V
1.1 V
V
V
V
V
C2
C2
C2
C2
CCL
CCL
CCL
CCL
=
=
=
=
3.127
3.127
3.188
3.025
2.811
2.811
2.874
2.711
1.1 V
1.1 V
1.1 V
1.1 V
V
V
V
V
C3
C3
C3
C3
CCL
CCL
CCL
CCL
list the global clock timing parameters for EP3SE80
list the regional clock timing parameters for EP3SE80
=
=
=
=
3.524
3.524
3.552
3.371
3.171
3.171
3.205
3.024
1.1 V
1.1 V
1.1 V
1.1 V
V
V
V
V
C4
C4
C4
C4
CCL
CCL
CCL
CCL
=
=
=
=
-0.199
-0.199
-0.171
-0.342
-0.187
-0.187
-0.167
-0.338
3.430
3.430
3.446
3.275
3.087
3.087
3.107
2.936
1.1 V
1.1 V
1.1 V
1.1 V
V
V
V
V
CCL
CCL
CCL
CCL
=
=
=
=
C4L
C4L
C4L
C4L
-0.042
-0.042
-0.221
-0.380
-0.030
-0.030
-0.229
-0.388
3.989
3.989
3.769
3.610
3.547
3.547
3.332
3.173
0.9 V
0.9 V
0.9 V
0.9 V
V
V
V
V
CCL
CCL
CCL
CCL
=
=
=
=
-0.315
-0.315
-0.199
-0.369
-0.303
-0.303
-0.210
-0.380
3.127
3.127
3.258
3.089
2.811
2.811
2.938
2.768
1.1 V
1.1 V
1.1 V
1.1 V
V
V
V
V
I3
CCL
I3
CCL
I3
CCL
I3
CCL
Stratix III Device Handbook, Volume 2
=
=
=
=
-0.292
-0.292
-0.173
-0.362
-0.280
-0.280
-0.169
-0.358
3.524
3.524
3.633
3.444
3.171
3.171
3.277
3.088
1.1 V
1.1 V
1.1 V
1.1 V
V
V
V
V
I4
CCL
I4
CCL
I4
CCL
I4
CCL
=
=
=
=
-0.199 -0.042
-0.199 -0.042
-0.121 -0.266
-0.300 -0.425
-0.187 -0.030
-0.187 -0.030
-0.118 -0.275
-0.297 -0.434
3.430
3.430
3.515
3.336
3.087
3.087
3.169
2.990
1.1 V
1.1 V
1.1 V
1.1 V
V
V
V
V
CCL
CCL
CCL
CCL
=
=
=
=
I4L
I4L
I4L
I4L
3.989
3.989
3.813
3.654
3.547
3.547
3.373
3.214
0.9 V
0.9 V
0.9 V
0.9 V
V
V
V
V
1–321
CCL
CCL
CCL
CCL
=
=
=
=
Units
Units
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns