EP3SL150F780C2N Altera, EP3SL150F780C2N Datasheet - Page 146
EP3SL150F780C2N
Manufacturer Part Number
EP3SL150F780C2N
Description
IC STRATIX III FPGA 150K 780FBGA
Manufacturer
Altera
Series
Stratix® IIIr
Datasheets
1.EP3SL150F780C4N.pdf
(16 pages)
2.EP3SL150F780C4N.pdf
(332 pages)
3.EP3SL150F780C4N.pdf
(456 pages)
4.EP3SL150F780C2N.pdf
(341 pages)
Specifications of EP3SL150F780C2N
Number Of Logic Elements/cells
142500
Number Of Labs/clbs
5700
Total Ram Bits
6390
Number Of I /o
488
Voltage - Supply
0.86 V ~ 1.15 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Family Name
Stratix III
Number Of Logic Blocks/elements
142500
# I/os (max)
488
Frequency (max)
600MHz
Process Technology
65nm
Operating Supply Voltage (typ)
1.1V
Logic Cells
142500
Ram Bits
6543360
Operating Supply Voltage (min)
1.05V
Operating Supply Voltage (max)
1.15V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
For Use With
544-2568 - KIT DEVELOPMENT STRATIX III
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2405
EP3SL150F780C2NES
EP3SL150F780C2NES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3SL150F780C2N
Manufacturer:
ALTERA
Quantity:
200
Part Number:
EP3SL150F780C2N
Manufacturer:
ALTERA
Quantity:
20 000
- EP3SL150F780C4N PDF datasheet
- EP3SL150F780C4N PDF datasheet #2
- EP3SL150F780C4N PDF datasheet #3
- EP3SL150F780C2N PDF datasheet #4
- Current page: 146 of 332
- Download datasheet (4Mb)
1–146
Table 1–79. EP3SL150 Column Pin Delay Adders for Regional Clock
Table 1–80. EP3SL150 Row Pin Delay Adders for Regional Clock
Table 1–81. EP3SL200 Column Pins Input Timing Parameters (Part 1 of 4)
Stratix III Device Handbook, Volume 2
RCLK input adder
RCLK PLL input adder
RCLK output adder
RCLK PLL output adder
RCLK input adder
RCLK PLL input adder
RCLK output adder
RCLK PLL output adder
3.3-V
LVTTL
3.3-V
LVCMOS
Standard
I/O
Parameter
Parameter
GCLK
GCLK
GCLK
GCLK
Clock
PLL
PLL
t
t
t
t
t
t
t
t
Table 1–79
must be added to the GCLK values. Use these adder values to determine I/O timing
when the I/O pin is driven using the regional clock. This applies to all I/O standards
supported by Stratix III devices.
Table 1–79
Table 1–80
EP3SL200 I/O Timing Parameters
Table 1–81
devices for single-ended I/O standards.
Table 1–81
I/O standards.
su
su
su
su
h
h
h
h
Industrial
-0.374
-2.017
0.198
2.453
Industrial
Industrial
-0.093
-0.063
0.107
0.074
-1.137
-1.465
-1.137
-1.465
1.285
1.778
1.285
1.778
Fast Model
Fast Model
Fast Model
through
and
lists the EP3SL150 column pin delay adders when using the regional clock.
lists the EP3SL150 row pin delay adders when using the regional clock.
lists the EP3SL200 column pins input timing parameters for single-ended
Commercial
Commercial
-0.152
-1.798
Commercial
0.152
2.426
-0.103
-0.065
Table 1–80
0.115
0.075
-1.173
-1.465
-1.173
-1.465
1.319
1.778
1.319
1.778
Table 1–84
-0.216 -0.232 -0.248
1.1 V
3.654
-2.68
V
0.22
C2
-0.137 -0.136 -0.133 -0.134 -0.257 -0.125 -0.121 -0.122 -0.261
-0.097 -0.102 -0.103 -0.102 -0.198 -0.088 -0.089 -0.088 -0.202
CCL
-1.810 -1.775 -2.002 -1.934 -2.482 -1.775 -2.002
-2.238 -2.271 -2.558 -2.477 -2.997 -2.271 -2.558
-1.810 -1.775 -2.002 -1.934 -2.482 -1.775 -2.002
-2.238 -2.271 -2.558 -2.477 -2.997 -2.271 -2.558
0.164
0.116
2.032
2.727
2.032
2.727
1.1 V
V
1.1 V
V
list the EP3SL150 regional clock (RCLK) adder values that
C2
CCL
C2
=
CCL
=
=
list the maximum I/O timing parameters for EP3SL200
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
-2.859 -3.011
0.258
4.098
1.1 V
V
C3
2.008
2.776
2.008
2.776
CCL
0.165
0.123
1.1 V
1.1 V
V
V
C3
C3
CCL
CCL
=
=
=
4.422
1.1 V
V
0.27
2.259
3.113
2.259
3.113
0.167
0.129
C4
1.1 V
CCL
1.1 V
V
V
C4
C4
CCL
CCL
=
=
=
-0.227
-2.872
0.262
4.224
1.1 V
V
2.177
3.000
2.177
3.000
0.165
0.126
1.1 V
1.1 V
V
V
CCL
CCL
CCL
=
=
=
C4L
C4L
C4L
-0.367
-2.715
0.393
4.664
0.9 V
V
2.724
3.543
2.724
3.543
0.285
0.218
0.9 V
0.9 V
V
V
CCL
CCL
CCL
=
=
=
© July 2010 Altera Corporation
-2.714
0.244
4.106
-0.11
1.1 V
0.158
0.114
2.008
2.776
2.008
2.776
V
1.1 V
1.1 V
V
V
CCL
I3
CCL
CCL
I3
I3
=
=
=
-0.127 -0.106 -0.303
-3.082 -2.791 -2.766
0.271
4.447
0.159
0.118
1.1 V
1.1 V
2.259
3.113
2.259
3.113
V
V
1.1 V
V
CCL
CCL
I4
I4
I4
CCL
=
=
=
0.158
0.114
I/O Timing
0.261
4.101
1.1 V
-1.934
-2.477
-1.934
-2.477
V
1.1 V
2.177
3.000
2.177
3.000
V
1.1 V
V
CCL
CCL
CCL
=
=
=
I4L
I4L
I4L
0.223
0.9 V
V
0.29
0.495
4.707
-2.482
-2.997
-2.482
-2.997
0.9 V
V
2.724
3.543
2.724
3.543
0.9 V
CCL
V
CCL
CCL
=
=
=
Units
Units
ns
ns
ns
ns
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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