EP2SGX90EF1152C5N Altera, EP2SGX90EF1152C5N Datasheet - Page 109
EP2SGX90EF1152C5N
Manufacturer Part Number
EP2SGX90EF1152C5N
Description
IC STRATIX II GX 90K 1152-FBGA
Manufacturer
Altera
Series
Stratix® II GXr
Datasheet
1.EP2SGX30DF780C5.pdf
(316 pages)
Specifications of EP2SGX90EF1152C5N
Number Of Logic Elements/cells
90960
Number Of Labs/clbs
4548
Total Ram Bits
4520448
Number Of I /o
558
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 70°C
Package / Case
1152-FBGA
For Use With
544-1725 - PCIE KIT W/S II GX EP2SGX90N544-1724 - SI KIT W/SII GX EP2SGX90N544-1702 - VIDEO KIT W/SII GX EP2SGX90N
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-1768
EP2SGX90EF35C5NES
EP2SGX90EF35C5NES
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Manufacturer
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Figure 2–71. Global and Regional Clock Connections from Center Clock Pins and Fast PLL Outputs
(2)
Notes to
(1)
(2)
Altera Corporation
October 2007
CLK0
CLK1
CLK2
CLK3
EP2SGX30C/D and P2SGX60C/D devices only have two fast PLLs (1 and 2) and two Enhanced PLLs (5 and 6), but
the connectivity from these PLLs to the global and regional clock networks remains the same as shown.
The global or regional clocks in a fast PLL’s quadrant can drive the fast PLL input. A dedicated clock input pin or
other PLL must drive the global or regional source. The source cannot be driven by internally generated logic before
driving the fast PLL.
Figure
2–71:
PLL 1
PLL 2
Fast
Fast
C0
C1
C2
C3
C0
C1
C2
C3
RCLK0
RCLK1
RCLK2
RCLK3
RCLK4
RCLK5
RCLK6
RCLK7
Stratix II GX Device Handbook, Volume 1
GCLK0
GCLK1
Stratix II GX Architecture
GCLK2
GCLK3
Notes
Signal Input
Logic Array
To Clock
Network
2–101
(1),
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